VSC056KM datasheet(14/134 Pages) MAXIM

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VSC056

Data Sheet

Revision 4.1

January 2008

The VSC056 device can operate at frequencies other than those listed in the above table and maintain

accurate fan speed and LED control frequencies, as well as continue to meet both the Standard mode

(100 kHz) and Fast mode (400 kHz) serial interface timings. Frequencies from 8.0 MHz to 12.5 MHz and

32.0 MHz to 75.0 MHz are allowable as long as they meet the AC timing requirements. For information on

AC timing requirements, see “AC Characteristics,” page 119.

The Clock Divider Control Register (CDC), located at FEh, can be programmed to override the divider

value selected by the CKSEL input pins and adjust the divided clock source used for the fan speed and

LED control logic. The pulse-width modulated outputs are not controlled by this logic and can vary based

on the input frequency. For examples of various frequency settings, based on both the CKSEL inputs and

the appropriate CDC register value, see“FEh: Clock Divider Control (CDC),” page 113.

Logic within the VSC056 synchronizes the divided clocks between devices attached to the same two-wire

serial bus with no more than 200 ns of skew when the fixed divider frequencies are used. Multiple devices

can then be used to drive different LEDs at the same frequency, providing a synchronized visible

indication. Devices attached to different two-wire serial busses can be synchronized by enabling the

SYNC# pin. This pin, which is connected to the SYNC# pin of all VSC056 devices in the system, provides

a sync pulse based on a programmable delay that is greater than the slowest selected LED flash rate. For

more information about the programmable capabilities of this feature, see “FDh: Clock Select Control

(CSC),” page 111.

2.5

Power-on Reset

Power-on reset (POR) is accomplished by the use of an internal POR cell. The external RESET# pin

provides the ability to reset the two-wire serial interface core, allowing for easy recovery of the two-wire

serial bus after a warm restart or at any time deemed appropriate within the system. If the external

RESET# pin is used, it can be driven by a power supply supervisor circuit, a reset pulse sourced from

another device, or a simple circuit composed of a resistor, a capacitor, and a diode. The external reset

source does not have to be synchronous to the VSC056 clock input. If the external resistor-capacitor-diode

circuit is used, the components selected must be able to provide a valid LOW to HIGH transition after VDD

is stable. If the RESET# pin is not used, it must be connected to VDD. After power on, the serial interface

state machine always returns an idle state while waiting for a START condition to appear on the SCL and

SDA pins. A proper power-on reset sequence clears the serial interface state machine, the clock generators,

the control registers, the I/O control logic, and the port bypass control logic. The divided clocks used for

LED flash rate generation are also in a known state. Regardless of the effectiveness of the power-on reset

mechanism, it is strongly recommended that the control registers and the I/O control logic be cleared

through the Soft Reset register bit. This can be accomplished by writing a 80h to the BCT Register (FCh),

followed immediately by a two-wire STOP condition. This bit is self-resetting and does not require further

attention.

VSC056KM Datasheet(PDF) 14 Page - Maxim Integrated Products