DS3141 datasheet(28/88 Pages) MAXIM

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DS3141/DS3142/DS3143/DS3144 Single/Dual/Triple/Quad DS3/E3 Framers

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7.6.1 Master Status Register (MSR)

The master status register (MSR) is a special status register that helps the host processor quickly locate changes

in device status. Each major block in the framer has a status bit in the MSR. When an alarm or event occurs in one

of these blocks, the device can be configured to set the appropriate bit in the MSR. The latched status bits in the

MSRL can also cause a hardware interrupt to occur. In both interrupt-based and polling-based device servicing

strategies, the host processor should read the ISR1 register to determine which framers need service and then

read the MSRL register of each framer that needs service to determine which blocks within the framer need

service.

MSR

Master Status Register

08h

Bit #

Name

LORC

LOTC

T3E3

FEAC

HDLC

BERT

COVF

N/A

Default

—

Bit 1: Counter Overflow Event (COVF). This real-time status bit is set to 1 if any of the error counters saturate

(the error counters saturate when full). This bit is cleared when the error counters are cleared. The error counters

are discussed in Section 7.8.

Bit 2: Change in BERT Status (BERT). This real-time status bit is set when any of the bits in the BSRL register

are set and the corresponding bits in the BSRIE interrupt-enable register are set. This bit is cleared when the

latched status bits in the BSRL register are cleared or the interrupt-enable bits in the BSRIE register are cleared.

The setting of this status bit can cause a hardware interrupt to occur if the BERTIE bit in the MSRIE register is set

to 1. The interrupt is cleared when this bit is cleared or the interrupt-enable bit in the MSRIE register is cleared.

Bit 3: Change in HDLC Status (HDLC). This real-time status bit is set when any of the bits in the HSRL register

are set and the corresponding bits in the HSRIE interrupt-enable register are set. This bit is cleared when the

latched status bits in the HSRL register are cleared or the interrupt-enable bits in the HSRIE register are cleared.

The setting of this status bit can cause a hardware interrupt to occur if the HDLCIE bit in the MSRIE register is set

to 1. The interrupt is cleared when this bit is cleared or the interrupt-enable bit in the MSRIE register is cleared.

Bit 4: Change in FEAC Status (FEAC). This real-time status bit is set when any of the bits in the FSRL register

are set and the corresponding bits in the FSRIE interrupt-enable register are set. This bit is cleared when the

latched status bits in the FSRL register are cleared or the interrupt-enable bits in the FSRIE register are cleared.

The setting of this status bit can cause a hardware interrupt to occur if the FEACIE bit in the MSRIE register is set

to 1. The interrupt is cleared when this bit is cleared or the interrupt-enable bit in the MSRIE register is cleared.

Bit 5: Change in DS3/E3 Framer Status (T3E3). This real-time status bit is set when any of the bits in the

T3E3SRL register are set and the corresponding bits in the T3E3SRIE interrupt-enable register are set. This bit is

cleared when the latched status bits in the T3E3SRL register are cleared or the interrupt-enable bits in the

T3E3SRIE register are cleared. The setting of this status bit can cause a hardware interrupt to occur if the T3E3IE

bit in the MSRIE register is set to 1. The interrupt is cleared when this bit is cleared or the interrupt-enable bit in the

MSRIE register is cleared.

Bit 6: Loss-of-Transmit Clock Detected (LOTC). This real-time status bit is set when the device detects that the

TICLK input pin has not toggled for between 9 and 21 clock periods. This bit is cleared when a clock is detected at

the TICLK input. The system clock (SCLK) is used to check for the presence of the TICLK. On reset the LOTC

status bit is set for a few clock cycles and then cleared if TICLK is present.

Bit 7: Loss-of-Receive Clock Detected (LORC). This real-time status bit is set when the device detects that the

RCLK input pin has not toggled for between 9 and 21 clock periods. This bit is cleared when a clock is detected at

the RCLK input. The system clock (SCLK) checks for the presence of the RCLK. On reset the LORC status bit is

set for a few clock cycles and then cleared if RCLK is present.

DS3141 Datasheet(PDF) 28 Page - Maxim Integrated Products

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