DS3141 datasheet(46/88 Pages) MAXIM

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DS3141/DS3142/DS3143/DS3144 Single/Dual/Triple/Quad DS3/E3 Framers

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BCR1

BERT Control Register 1

30h

Bit #

Name

BM1

BM0

BENA

TINV

RINV

RESYNC

Default

Bit 0: Load Bit and Error Counts (LC). A low-to-high transition latches the current bit and error counts into the

host-processor-accessible registers BBCR and BBECR and then clears the internal counters. This bit should be

toggled from low to high whenever the host processor wishes to begin a new acquisition period. Must be cleared

and set again for subsequent loads.

Bit 1: Transmit Pattern Load (TC). A low-to-high transition loads the pattern generator. This bit should be toggled

from low to high whenever the host processor loads a new pattern or needs to resynchronize to an existing pattern.

Must be cleared and set again for subsequent loads. For pseudorandom patterns, PS[2:0] must be configured

before toggling TC. For repetitive patterns, PS[2:0], RPL[3:0], and RP[31:0] must be configured before toggling TC.

For alternating word patterns, PS[2:0], AWC[7:0], and RP[31:0] must be configured before toggling TC.

Bit 2: Force Resynchronization (RESYNC). A low-to-high transition forces the receive BERT synchronizer to

resynchronize to the incoming data stream. This bit should be toggled from low to high whenever the host

processor wishes to acquire synchronization on a new pattern. Must be cleared and set again for a subsequent

resynchronization.

Bit 3: Receive Invert Data Enable (RINV)

0 = do not invert the incoming data stream

1 = invert the incoming data stream

Bit 4: Transmit Invert Data Enable (TINV)

0 = do not invert the outgoing data stream

1 = invert the outgoing data stream

Bit 5: BERT Enable (BENA). This bit is used to enable the BERT transmitter, replacing the payload, or the entire

DS3/E3 signal (depending on the setting of BM[1:0]). The BERT receiver is always enabled. Configure all BERT

control and pattern registers and toggle the TC control bit before setting BENA.

0 = disable BERT transmitter

1 = enable BERT transmitter

Bits 6, 7: BERT Mode (BM[1:0]). These bits select whether the BERT pattern replaces only the DS3/E3 payload

or the entire DS3/E3 frame (payload and overhead). These bits also select the BERT transmit direction: line side

(TPOS/TNEG and RPOS/RNEG) or equipment side (TDAT and RDAT).

BM[1:0]

DATA

TRANSMIT

RECEIVE

Payload

TPOS/TNEG

RPOS/RNEG

Entire frame

TPOS/TNEG

RPOS/RNEG

Payload

RDAT

TDAT

Entire frame

RDAT

TDAT

DS3141 Datasheet(PDF) 46 Page - Maxim Integrated Products

DS3141 Datasheet(HTML) 46 Page - Maxim Integrated Products

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