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MSRL

Master Status Register Latched

09h

Bit #

Name

LORCL

LOTCL

N/A

COVFL

OSTL

Default

—

Note: See Figure 7-4 for details on the interrupt logic for the status bits in the MSRL register.

Bit 0: One-Second Timer Latched (OSTL). This latched status bit is set to 1 on each 1-second boundary, as

timed by the device. The device chooses an arbitrary 1-second boundary that is timed from either the RCLK signal

or the TICLK signal depending on the setting of the OSTCS bit in MC2. OSTL is cleared when the host processor

writes a 1 to it and is not set again until another 1-second boundary has occurred. When OSTL is set, it can cause

a hardware interrupt to occur if the OSTIE bit in the MSRIE register is set to 1. The interrupt is cleared when this bit

is cleared or the interrupt-enable bit is cleared. This bit can be used to determine when to read the error counters, if

the counters are automatically updated by the 1-second timer.

Bit 1: Counter Overflow Event Latched (COVFL). This latched status bit is set to 1 when the COVF status bit in

the MSR register goes high. COVFL is cleared when the host processor writes a 1 to it and is not set again until

COVF goes high again. When COVFL is set, it can cause a hardware interrupt to occur if the COVFIE bit in the

MSRIE register is set to 1. The interrupt is cleared when this bit is cleared or the interrupt-enable bit is cleared. This

bit can be used to determine when a counter overflow event occurs.

Bit 6: Loss-of-Transmit Clock Latched (LOTCL). This latched status bit is set to 1 when the LOTC status bit in

the MSR register goes high. LOTCL is cleared when the host processor writes a 1 to it and is not set again until

LOTC goes high again. When LOTCL is set, it can cause a hardware interrupt to occur if the LOTCIE bit in the

MSRIE register is set to 1. The interrupt is cleared when this bit is cleared or the interrupt-enable bit is cleared. This

bit can be used to determine when a loss of transmit clock event occurs.

Bit 7: Loss-of-Receive Clock Latched (LORCL). This latched status bit is set to 1 when the LORC status bit in

the MSR register goes high. LORCL is cleared when the host processor writes a 1 to it and is not set again until

LORC goes high again. When LORCL is set, it can cause a hardware interrupt to occur if the LORCIE bit in the

MSRIE register is set to 1. The interrupt is cleared when this bit is cleared or the interrupt-enable bit is cleared. This

bit can be used to determine when a loss of receive clock event occurs.

DS3141 Datasheet(PDF) 29 Page - Maxim Integrated Products