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PCA8802 Datasheet(PDF) 17 Page - NXP Semiconductors

Part # PCA8802
Description  ultra low power oscillator with integrated counter for initiating one time password generation
PDF  34 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

PCA8802 Datasheet(HTML) 17 Page - NXP Semiconductors

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PCA8802_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 19 February 2009
17 of 34
NXP Semiconductors
PCA8802
Smartcard RTC
This instruction takes only 3 parameters in one command. Data after the 3rd parameter
will be interpreted as the next instruction.
Accurate setting and start-up can be implemented using the dvs_cmd instruction in
cooperation with the set_cmd instruction. An example is shown in Table 8.
9.6.8 Instruction rd_cmd
With the read instruction (rd_cmd) the counter value can be read at any time. When the
counter value is read, the counter is frozen so that there will be no changes during the
read back. After a read is terminated, the counter will be allowed to increment again. Any
increment that was scheduled during the frozen period will then be effected.
Reading the counter is cyclic i.e. the device will repeatedly return the present counter
value until the read is terminated. Reading the counter more than once may be useful in
the case that the application is subject to a strong Electromagnetic Interference (EMI)
environment so that read back values can be compared.
Read back must be terminated within 32 seconds else a count will be dropped.
Table 8.
Example of accurate setting of the counter
Step
Action
Code sequence Note
1
initiate transfer
START condition -
2
send wrt_cmd
1010 0000
-
3
enable dvs_cmd
0001 0001
-
4
set counter with set_cmd
1000 0000
set the counter = 1
0000 0000
P1[23:16]
0000 0000
P2[15:8]
0000 0001
P3[7:0]
5
end transfer
STOP condition
-
6
wait for an external time
marker
--
7
initiate transfer
START condition -
8
send wrt_cmd
1010 0000
-
9
disable dvs_cmd
0001 0000
counter starts on the ACK cycle of this
instruction
10
end transfer
STOP condition
-
Fig 25. Read bit order
001aaj208
b23 b22
MSB
b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
LSB



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