PCF8532 datasheet(23/44 Pages) NXP

23 / 44 page

PCF8532_1

Product data sheet

Rev. 1 — 10 February 2009

23 of 44

NXP Semiconductors

PCF8532

Universal LCD driver for low multiplex rates

[1]

Power-on and reset value.

[2]

The possibility to disable the display allows implementation of blinking under external control; the enable bit

determines also wether the internal clock signal is available at the CLK pin (see Section 7.5.1).

[1]

Power-on and reset value.

[1]

Power-on and reset value.

Table 8.

Deﬁnition of PCF8532 commands

Command

Operation code

Reference

Bit

mode-set

Table 9

load-data-pointer-MSB

Table 10

load-data-pointer-LSB

Table 11

device-select

Table 12

bank-select

Table 13

blink-select

BF1

BF0

Table 14

frequency-prescaler

Table 15

Table 9.

Mode-set command bits description

Bit

Symbol

Value

Description

7 to 4

1100

ﬁxed value

display status

0[1]

disabled (blank)[2]

enabled

LCD bias conﬁguration

0[1]

⁄3 bias

⁄2 bias

1 to 0

M[1:0]

LCD drive mode selection

static; BP0

1:2 multiplex; BP0, BP1

1:3 multiplex; BP0, BP1, BP2

00[1]

1:4 multiplex; BP0, BP1, BP2, BP3

Table 10.

Load-data-pointer-MSB command bits description

Bit

Symbol

Value

Description

7 to 4

0000

ﬁxed value

3 to 0

P[7:4]

0000[1] to

1001

P7 to P4 deﬁnes the ﬁrst 4 (most signiﬁcant) bits of

the data pointer that indicates one of the 160 display

RAM addresses

Table 11.

Load-data-pointer-LSB command bits description

Bit

Symbol

Value

Description

7 to 4

0100

ﬁxed value

3 to 0

P[3:0]

0000[1] to

1111

P3 to P0 deﬁnes the last 4 (least signiﬁcant) bits of the

data pointer that indicates one of the 160 display RAM

addresses

PCF8532 Datasheet(PDF) 23 Page - NXP Semiconductors

PCF8532 Datasheet(HTML) 23 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

Datasheet Download

Link URL