PCF8532 datasheet(15/44 Pages) NXP

15 / 44 page

PCF8532_1

Product data sheet

Rev. 1 — 10 February 2009

15 of 44

NXP Semiconductors

PCF8532

Universal LCD driver for low multiplex rates

• In 1:3 multiplex mode the bits are placed in row 0, 1 and 2 to three successive

addresses, with bit 2 of the third address left unchanged. This last bit may, if

necessary, be controlled by an additional transfer to this address but care should be

taken to avoid overwriting adjacent data because always full bytes are transmitted.

• In the 1:4 multiplex mode the eight transmitted data bits are placed in

row 0, 1, 2 and 3 to two successive display RAM addresses.

7.11 Data pointer

The addressing mechanism for the display RAM is realized using the data pointer.

This allows the loading of an individual display data byte, or a series of display data bytes,

into any location of the display RAM. The sequence commences with the initialization of

the data pointer by the load-data-pointer-MSB and load-data-pointer-LSB commands.

Following this two commands, an arriving data byte is stored starting at the display RAM

address indicated by the data pointer. The ﬁlling order is shown in Figure 10.

The data pointer is automatically incremented in accordance with the chosen LCD

conﬁguration.

The contents of the data pointer are incremented as follows:

• In static drive mode by eight

• In 1:2 multiplex drive mode by four

• In 1:3 multiplex drive mode by three

• In 1:4 multiplex drive mode by two

If the data pointer reaches 159 it is automatically wrapped around to address 0,

consequently the subaddress counter is incremented.

If an I2C-bus data access is terminated early then the state of the data pointer is unknown.

The data pointer must be re-written prior to further RAM accesses.

The display RAM bitmap shows the direct relationship between the display RAM addresses and

the segment outputs; and between the bits in a RAM word and the backplane outputs.

Fig 9.

Display RAM bitmap

155 156 157 158 159

display RAM addresses (columns)/segment outputs (S)

display RAM bits

(rows)/

backplane outputs

(BP)

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