PCF8532 datasheet(30/44 Pages) NXP

30 / 44 page

PCF8532_1

Product data sheet

Rev. 1 — 10 February 2009

30 of 44

NXP Semiconductors

PCF8532

Universal LCD driver for low multiplex rates

11. Dynamic characteristics

[1]

Typical output duty factor: 50 % measured at the CLK output pin.

[2]

For fclk(ext) > 4 kHz it is recommended to use an external pull-up resistor between pin SYNC and pin VDD. The value of the resistor

should be between 100 k

Ω and 1 MΩ. This resistor should be present even when no cascading conﬁguration is used!

[3]

All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an

input voltage swing of VSS to VDD.

Table 18.

Dynamic characteristics

VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 8.0 V; Tamb = −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fclk

clock frequency

on pin CLK; see Table 15

[1]

900

1800

3000

fclk(ext)

external clock frequency

[2]

700

5000

tclk(H)

HIGH-level clock time

external clock source used

100

µs

tclk(L)

LOW-level clock time

external clock source used

100

µs

tPD(SYNC_N)

SYNC propagation delay

tSYNC_NL

SYNC LOW time

100

µs

tPD(drv)

driver propagation delay

VLCD = 5 V

µs

Timing characteristics: I2C-bus

[3]

fSCL

SCL clock frequency

400

kHz

tBUF

bus free time between a

STOP and START condition

1.3

µs

tHD;STA

hold time (repeated) START

condition

0.6

µs

tSU;STA

set-up time for a repeated

START condition

0.6

µs

tVD;ACK

data valid acknowledge time

1.2

µs

tHIGH

HIGH period of the SCL clock

0.6

µs

tLOW

LOW period of the SCL clock

1.3

µs

fall time

of both SDA and SCL signals

0.3

µs

rise time

of both SDA and SCL signals

0.3

µs

capacitive load for each bus

line

400

tSU;DAT

data set-up time

200

tHD;DAT

data hold time

tSU;STO

set-up time for STOP

condition

0.6

µs

tw(spike)

spike pulse width

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