82567 datasheet(28/33 Pages) INTEL

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82567—Datasheet

4.8

Timing Parameters

4.8.1

Timing Requirements

The 82567 requires the following start-up and power state transitions.

Table 10.

Timing Requirements

4.8.2

Timing Guarantees

The 82567 guarantees the following start-up and power state transition related timing

parameters.

Table 11.

Timing Guarantees

Parameter

Description

Min

Max

Notes

TJRST_min

Minimum duration of

JRSTSYNC pulse

1 ms

Per LCI specification

Tc2dud

Completion of dock/undock

configuration following cable

connection

0.5 sec

Tr2init

Completion of PHY

configuration following a reset

complete indication

0.5 sec

Parameter

Description

Min

Max

Notes

TPHY_Reset

Reset de-assertion to PHY

reset complete

10 ms

PHY configuration

should be delayed

until PHY completes

its reset

TXTAL

XTAL frequency stable after

platform power ramp up

5 ms

TPOR

Internal POR trigger after XTAL

stable

1 s

TJKCLK

JKCLK output stable after

internal POR

3 s

TTX_IDLE-TO-DIFF-DATA

Maximum time to transition to

valid TX specifications after

leaving an electrical idle

condition

200 ns

Required by GLCI

2.0 specification

TRX_IDLE-TO-DIFF-DATA

Maximum time to be ready to

accept data after leaving an

electrical idle condition

200 ns

Required by GLCI

2.0 specification

Tc2an

Cable connect to start of auto

negotiation

1.2 s

1.3 s

Per 802.3

specification

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