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FS714X Datasheet(PDF) 16 Page - ON Semiconductor |
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FS714X Datasheet(HTML) 16 Page - ON Semiconductor |
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16 / 19 page  FS714x Table 13: AC Timing Specifications Parameter Symbol Conditions/Description Clock (MHz) Min. Typ. Max. Units Overall CMOS outputs 0 150 Output frequency* fo(max) PECL outputs 0 300 MHz VCO frequency* fVCO 40 400 MHz CMOS mode rise time* tr CL = 7pF 1 ns CMOS mode fall time* tf CL = 7pF 1 ns PECL mode rise time* tr CL = 7pF; RL = 65 ohm 1 ns PECL mode fall time* tf CL = 7pF; RL = 65 ohm 1 ns Reference Frequency Input (REF) Input frequency FREF 80 MHz Reference high time tREHF 3 ns Reference low time tREFL 3 ns Sync Control Input (SYNC) Sync high time tSYNCH For orderly CLK stop/start 3 TCLK Sync low time tSYNCL For orderly CLK stop/start 3 TCLK Clock Output (CLKP, CLKN) Duty cycle (CMOS mode)* Measured at 1.4V 50 % Duty cycle (PECL mode)* Measured at zero crossings of (VCLKP – VCLKN) 50 % For valid programming solutions. Long-term (or cumulative) jitter specified is RMS position error of any edge compared with an ideal clock generated from the same reference frequency. It is measured with a time interval analyzer using a 500 microsecond window, using statistics gathered over 1000 samples. ps FREF/NREF > 1000kHz 25 ps FREF/NREF ~= 500kHz 50 ps FREF/NREF ~= 250kHz 100 ps FREF/NREF ~= 125kHz 190 ps FREF/NREF ~= 62.5kHz 240 ps Jitter, long term ( σy(τ))* tj(LT) FREF/NREF ~= 31.5kHz 300 ps 40MHz < VCO frequency <100MHz 75 ps Jitter, period (peak-peak)* tj(ΔP) VCO frequency > 100MHz 50 ps Unless otherwise stated, VDD = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. MIN and MAX characterization data are ± 3 σ from typical. Table 14: Serial Interface Timing Specifications Parameter Symbol Conditions/Description Fast Mode Units Min. Max. Clock frequency fSCL SCL 0 400 kHz Bus free time between STOP and START tBUF 1300 ns Set-up time, START (repeated) Tsu:STA 600 ns Hold time, START thd:STA 600 ns Set-up time, data input Tsu:DAT SDA 100 ns Hold time, data input thd:DAT SDA 0 ns Output data valid from clock tAA 900 ns Rise time, data and clock tR SDA, SCL 300 ns Fall time, data and clock tF SDA, SCL 300 ns High time, clock tHI SCL 600 ns Low time, clock tLO SCL 1300 ns Set-up time, STOP Tsu:STO 600 ns Unless otherwise stated, VDD = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. MIN and MAX characterization data are ± 3 σ from typical. Rev. 5 | Page 16 of 19 | www.onsemi.com |
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