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R28 Datasheet(PDF) 368 Page - Renesas Technology Corp |
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R28 Datasheet(HTML) 368 Page - Renesas Technology Corp |
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368 / 473 page ![]() R8C/28 Group, R8C/29 Group 19. Flash Memory Rev.2.10 Sep 26, 2008 Page 349 of 441 REJ09B0279-0210 Figure 19.5 FMR0 Register Flash Memory Control Register 0 Symbol Address After Reset FMR0 01B7h 00000001b Bit Symbol Bit Name Function RW RY/BY ___ status flag NOTES: 1. 2. 3. 4. 5. 6. This bit is set to 0 by executing the clear status command. This bit is enabled w hen the FMR01 bit is set to 1 (CPU rew rite mode enabled). When the FMR01 bit is set to 0, w riting 1 to the FMSTP bit causes the FMSTP bit to be set to 1. The flash memory does not enter low -pow er consumption state nor is it reset. FMR06 To set this bit to 1, set it to 1 immediately after setting it first to 0. Do not generate an interrupt betw een setting the bit to 0 and setting it to 1. Enter read array mode and set this bit to 0. Set this bit to 1 immediately after setting it first to 0 w hile the FMR01 bit is set to 1. Do not generate an interrupt betw een setting the bit to 0 and setting it to 1. Set this bit by a program transferred to the RAM. Program status flag(4) 0 : Completed successfully 1 : Terminated by error Erase status flag(4) 0 : Completed successfully 1 : Terminated by error RW RO RO RO Reserved bits Set to 0. RW FMR02 RW RW — (b5-b4) FMR00 FMSTP b7 b6 b5 b4 00 0 : Enables flash memory operation 1 : Stops flash memory (enters low -pow er consumption state and flash memory is reset) FMR01 Block 0, 1 rew rite enable bit(2, 6) 0 : Busy (w riting or erasing in progress) 1 : Ready CPU rew rite mode select bit(1) 0 : CPU rew rite mode disabled 1 : CPU rew rite mode enabled When setting the FMR01 bit to 0 (CPU rew rite mode disabled), the FMR02 bit is set to 0 (disables rew rite). FMR07 b3 b2 b1 b0 0 : Disables rew rite 1 : Enables rew rite Flash memory stop bit(3, 5) |
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