R28 datasheet(228/473 Pages) RENESAS

228 / 473 page

R8C/28 Group, R8C/29 Group

14. Timers

Rev.2.10

Sep 26, 2008

Page 209 of 441

REJ09B0279-0210

Figure 14.56

TRCCR1 Register in PWM2 Mode

j = A, B, C, or D

BFC, BFD: Bits in TRCMR register

NOTE:

1. Do not set the TRCGRB and TRCGRC registers to the same value.

Table 14.23

Functions of TRCGRj Register in PWM2 Mode

Setting

PWM2 Output Pin

TRCGRA

−

General register. Set the PWM period.

TRCIOB pin

TRCGRB

−

General register. Set the PWM output change point.

TRCGRC

BFC = 0

General register. Set the PWM output change point (wait time

after trigger).

TRCGRD

BFD = 0

(Not used in PWM2 mode)

−

TRCGRD

BFD = 1

Buffer register. Set the next PWM output change point. (Refer to

14.3.3.2 Buffer Operation

TRCIOB pin

Timer RC Control Register 1

Symbol

Address

After Reset

TRCCR1

0121h

00h

Bit Symbol

Bit Name

Function

NOTES:

b3 b2

TOD

b1 b0

TOA

b7 b6 b5 b4

0 : Active level “H”

(Initial output “L”

“H” output by compare match in the

TRCGRC register

“L” output by compare match in the

TRCGRB register

1 : Active level “L”

(Initial output “H”

“L” output by compare match in the

TRCGRC register

“H” output by compare match in the

TRCGRB register

TOB

TRCIOA output level select bit(1)

TRCIOB output level select bit(1, 2)

TRCIOC output level select bit(1)

Disabled in the PWM2 mode

TOC

TRCIOD output level select bit(1)

If the pin function is set for w aveform output (refer to Table 7.7 and Table 7.8), the initial output level is output

w hen the TRCCR1 register is set.

TRC counter clear select bit

TCK2

Set to these bits w hen the TSTART bit in the TRCMR register is set to 0 (count stops).

CCLR

Count source select bits(1)

b6 b5 b4

0 0 0 : f1

0 0 1 : f2

0 1 0 : f4

0 1 1 : f8

1 0 0 : f32

1 0 1 : TRCCLK input rising edge

1 1 0 : fOCO40M

1 1 1 : Do not set.

0 : Disable clear (free-running operation)

1 : Clear by compare match in the

TRCGRA register

TCK0

TCK1

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