R28 datasheet(277/473 Pages) RENESAS

277 / 473 page

R8C/28 Group, R8C/29 Group

16. Clock Synchronous Serial Interface

Rev.2.10

Sep 26, 2008

Page 258 of 441

REJ09B0279-0210

Figure 16.8

Registers SSTDR and SSRDR

SS Transmit Data Register

Symbol

Address

After Reset

SSTDR

00BEh

FFh

Function

Store the transmit data.

The stored transmit data is transferred to the SSTRSR register and transmission is started

w hen it is detected that the SSTRSR register is empty.

When the next transmit data is w ritten to the SSTDR register during the data transmission from

the SSTRSR register, the data can be transmitted continuously.

When the MLS bit in the SSMR register is set to 1 (transfer data w ith LSB-first), the data in

w hich MSB and LSB are reversed is read, after w riting to the SSTDR register.

b7 b6 b5

SS Receive Data Register

Symbol

Address

After Reset

SSRDR

00BFh

FFh

NOTE:

1. The SSRDR register retains the data received before an overrun error occurs (ORER bit in the SSSR register set to 1

(overrun error)). When an overrun error occurs, the receive data may contain errors and therefore should be

discarded.

Store the receive data.(1)

The receive data is transferred to the SSRDR register and the receive operation is completed

w hen 1 byte of data has been received by the SSTRSR register. At this time, the next receive

operation is possible. Continuous reception is possible using registers SSTRSR and SSRDR.

Function

b3 b2 b1 b0

b7 b6 b5 b4

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