R28 datasheet(279/473 Pages) RENESAS

279 / 473 page

R8C/28 Group, R8C/29 Group

16. Clock Synchronous Serial Interface

Rev.2.10

Sep 26, 2008

Page 260 of 441

REJ09B0279-0210

16.2.1

Transfer Clock

The transfer clock can be selected from among seven internal clocks (f1/256, f1/128, f1/64, f1/32, f1/16, f1/8,

and f1/4) and an external clock.

When using clock synchronous serial I/O with chip select, set the SCKS bit in the SSMR2 register to 1 and

select the SSCK pin as the serial clock pin.

When the MSS bit in the SSCRH register is set to 1 (operates as master device), an internal clock can be

selected and the SSCK pin functions as output. When transfer is started, the SSCK pin outputs clocks of the

transfer rate selected by bits CKS0 to CKS2 in the SSCRH register.

When the MSS bit in the SSCRH register is set to 0 (operates as slave device), an external clock can be selected

and the SSCK pin functions as input.

16.2.1.1

Association between Transfer Clock Polarity, Phase, and Data

The association between the transfer clock polarity, phase and data changes according to the combination of the

SSUMS bit in the SSMR2 register and bits CPHS and CPOS in the SSMR register.

Figure 16.10 shows the Association between Transfer Clock Polarity, Phase, and Transfer Data.

Also, the MSB-first transfer or LSB-first transfer can be selected by setting the MLS bit in the SSMR register.

When the MLS bit is set to 1, transfer is started from the LSB and proceeds to the MSB. When the MLS bit is

set to 0, transfer is started from the MSB and proceeds to the LSB.

R28 Datasheet(PDF) 279 Page - Renesas Technology Corp