R28 datasheet(281/473 Pages) RENESAS

281 / 473 page

R8C/28 Group, R8C/29 Group

16. Clock Synchronous Serial Interface

Rev.2.10

Sep 26, 2008

Page 262 of 441

REJ09B0279-0210

16.2.2

SS Shift Register (SSTRSR)

The SSTRSR register is a shift register for transmitting and receiving serial data.

When transmit data is transferred from the SSTDR register to the SSTRSR register and the MLS bit in the

SSMR register is set to 0 (MSB-first), the bit 0 in the SSTDR register is transferred to bit 0 in the SSTRSR

SSTRSR register.

16.2.2.1

Association between Data I/O Pins and SS Shift Register

The connection between the data I/O pins and SSTRSR register (SS shift register) changes according to a

combination of the MSS bit in the SSCRH register and the SSUMS bit in the SSMR2 register. The connection

also changes according to the BIDE bit in the SSMR2 register.

Figure 16.11 shows the Association between Data I/O Pins and SSTRSR Register.

Figure 16.11

Association between Data I/O Pins and SSTRSR Register

SSTRSR register

SSO

SSI

• SSUMS = 0

(clock synchronous communication mode)

SSTRSR register

SSO

SSI

• SSUMS = 1 (4-wire bus communication mode),

BIDE = 0 (standard mode), and MSS = 0 (operates

as slave device)

SSTRSR register

SSO

SSI

• SSUMS = 1 (4-wire bus communication mode),

BIDE = 0 (standard mode), and MSS = 1 (operates as

master device)

SSTRSR register

SSO

SSI

• SSUMS = 1 (4-wire bus communication mode) and

BIDE = 1 (bidirectional mode)

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