R29 datasheet(147/473 Pages) RENESAS

147 / 473 page

R8C/28 Group, R8C/29 Group

12. Interrupts

Rev.2.10

Sep 26, 2008

Page 128 of 441

REJ09B0279-0210

12.6.5

Changing Interrupt Control Register Contents

(a) The contents of an interrupt control register can only be changed while no interrupt requests

corresponding to that register are generated. If interrupt requests may be generated, disable interrupts

before changing the interrupt control register contents.

(b) When changing the contents of an interrupt control register after disabling interrupts, be careful to

choose appropriate instructions.

Changing any bit other than IR bit

If an interrupt request corresponding to a register is generated while executing the instruction, the IR bit

may not be set to 1 (interrupt requested), and the interrupt request may be ignored. If this causes a

problem, use the following instructions to change the register: AND, OR, BCLR, BSET

Changing IR bit

If the IR bit is set to 0 (interrupt not requested), it may not be set to 0 depending on the instruction used.

Therefore, use the MOV instruction to set the IR bit to 0.

to (b) regarding changing the contents of interrupt control registers by the sample programs.

Sample programs 1 to 3 are for preventing the I flag from being set to 1 (interrupts enabled) before the interrupt

control register is changed for reasons of the internal bus or the instruction queue buffer.

Example 1:

Use NOP instructions to prevent I flag from being set to 1 before interrupt control register

is changed

INT_SWITCH1:

FCLR

; Disable interrupts

AND.B

#00H,0056H

; Set TRAIC register to 00h

NOP

;

NOP

FSET

; Enable interrupts

Example 2:

Use dummy read to delay FSET instruction

INT_SWITCH2:

FCLR

; Disable interrupts

AND.B

#00H,0056H

; Set TRAIC register to 00h

MOV.W MEM,R0

; Dummy read

FSET

; Enable interrupts

Example 3:

Use POPC instruction to change I flag

INT_SWITCH3:

PUSHC

FLG

FCLR

; Disable interrupts

AND.B

#00H,0056H

; Set TRAIC register to 00h

POPC

FLG

; Enable interrupts

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