R29 datasheet(150/473 Pages) RENESAS

150 / 473 page

R8C/28 Group, R8C/29 Group

13. Watchdog Timer

Rev.2.10

Sep 26, 2008

Page 131 of 441

REJ09B0279-0210

Figure 13.3

Registers WDTR, WDTS, and CSPR

Watchdog Timer Reset Register

Symbol

Address

After Reset

WDTR

000Dh

Undefined

NOTES:

When 00h is w ritten before w riting FFh, the w atchdog timer is reset.(1)

The default value of the w atchdog timer is 7FFFh w hen count source protection

mode is disabled and 0FFFh w hen count source protection mode is enabled.(2)

Function

Do not generate an interrupt betw een w hen 00h and FFh are w ritten.

When the CSPRO bit in the CSPR register is set to 1 (count source protection mode enabled),

0FFFh is set in the w atchdog timer.

Watchdog Timer Start Register

Symbol

Address

After Reset

WDTS

000Eh

Undefined

Function

The w atchdog timer starts counting after a w rite instruction to this register.

Count Source Protection Mode Register

Symbol

Address

After Reset(1)

CSPR

001Ch

00h

Bit Symbol

Bit Name

Function

NOTES:

CSPRO

Count Source Protection Mode

Select Bit(2)

0 : Count source protection mode disabled

1 : Count source protection mode enabled

—

(b6-b0)

000

b7 b6 b5 b4 b3 b2 b1 b0

Write 0 before w riting 1 to set the CSPRO bit to 1.

0 cannot be set by a program.

When 0 is w ritten to the CSPROINI bit in the OFS register, the value after reset is 10000000b.

Reserved Bits

Set to 0.

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