R29 datasheet(148/473 Pages) RENESAS

148 / 473 page

R8C/28 Group, R8C/29 Group

13. Watchdog Timer

Rev.2.10

Sep 26, 2008

Page 129 of 441

REJ09B0279-0210

13. Watchdog Timer

The watchdog timer is a function that detects when a program is out of control. Use of the watchdog timer is

recommended to improve the reliability of the system. The watchdog timer contains a 15-bit counter and allows

selection of count source protection mode enable or disable.

Table 13.1 lists information on the Count Source Protection Mode.

Refer to 5.7 Watchdog Timer Reset for details on the watchdog timer.

Figure 13.1 shows the Block Diagram of Watchdog Timer. Figure 13.2 shows Registers OFS and WDC. Figure 13.3

shows Registers WDTR, WDTS, and CSPR.

Figure 13.1

Block Diagram of Watchdog Timer

Table 13.1

Count Source Protection Mode

Item

Count Source Protection

Mode Disabled

Count Source Protection

Mode Enabled

Count source

CPU clock

Low-speed on-chip oscillator

clock

Count operation

Decrement

Count start condition

Either of the following can be selected

• After reset, count starts automatically

• Count starts by writing to WDTS register

Count stop condition

Stop mode, wait mode

None

Reset condition of watchdog

timer

• Reset

• Write 00h to the WDTR register before writing FFh

• Underflow

Operation at the time of underflow Watchdog timer interrupt or

watchdog timer reset

Watchdog timer reset

CPU clock

1/16

1/128

Watchdog timer

Internal

reset signal

Write to WDTR register

WDC7 = 0

WDC7 = 1

Set to

7FFFh(1)

PM12 = 1

Watchdog

timer reset

PM12 = 0

Watchdog timer

interrupt request

Prescaler

CSPRO = 0

fOCO-S

CSPRO = 1

CSPRO: Bit in CSPR register

WDC7: Bit in WDC register

PM12: Bit in PM1 register

NOTE:

1. When the CSPRO bit is set to 1 (count source protection mode enabled), 0FFFh is set.

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