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R5F36CAMDFB Datasheet(PDF) 83 Page - Renesas Technology Corp |
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R5F36CAMDFB Datasheet(HTML) 83 Page - Renesas Technology Corp |
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83 / 94 page ![]() REJ03B0277-0100 Rev.1.00 Jul.15, 2009 Page 81 of 90 M16C/6C Group 5. Electrical Characteristics Figure 5.16 Timing Diagram Memory Expansion Mode and Microprocessor Mode ( Effective in wait state setting) BCLK HOLD input HLDA input P0, P1, P2, P3, P4, P5_0 to P5_2 (1) (Common to wait state and no wait state settings) Note: 1. These pins are high-impedance regardless PM06 bit in PM0 register, and PM11 bit in PM1 register. Hi−Z RDY input RD BCLK (Separate bus) (Multiplexed bus) WR RD (Separate bus) WR (Multiplexed bus) tsu(RDY-BCLK) th(BCLK-RDY) tsu(HOLD-BCLK) th(BCLK-HOLD) td(BCLK-HLDA) td(BCLK-HLDA) Measuring conditions V = V = 3 V CC1 CC2 Input timing voltage: V = 0.6 V, V = 2.4 V IL IH Output timing voltage: V = 1.5 V, V = 1.5 V OL OH V = V = 3 V CC1 CC2 |
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