R5F36CAMDFB datasheet(16/94 Pages) RENESAS

16 / 94 page

REJ03B0277-0100 Rev.1.00 Jul.15, 2009

Page 14 of 90

M16C/6C Group

2. Central Processing Unit (CPU)

Central Processing Unit (CPU)

Figure 2.1 shows the CPU registers. Seven registers (R0, R1, R2, R3, A0, A1, and FB) out of 13 compose a

Figure 2.1

CPU Register

2.1

Data Registers (R0, R1, R2, and R3)

R0, R1, R2, and R3 are 16-bit registers used for transfer, arithmetic, and logic operations. R0 and R1 can

be split into high-order (R0H/R1H) and low-order (R0L/R1L) bits to be used separately as 8-bit data

registers.

R0 can be combined with R2, and R3 can be combined with R1 and be used as 32-bit data registers

R2R0 and R3R1, respectively.

R0H(high-order bitsof R0)

b15

b8 b7

INTBH

USP

ISP

Note:

1. These registers compose a register bank. There are two register banks.

IPL

b31

b19

INTBL

b15

INTBH is the 4 high-order bits of the INTB register

and INTBL is the 16 low-order bits.

b19

b15

FLG

b15

Data registers (1)

Address registers (1)

Frame base registers (1)

Program counter

Interrupt table register

User stack pointer

Interrupt stack pointer

Static base register

Flag register

Reserved area

Carry flag

Debug flag

Zero flag

Sign flag

Overflow flag

Interrupt enable flag

Stack pointer select flag

Reserved area

Processor interrupt priority level

R1H(high-order bitsof R1)

R0L(low-order bitsof R0)

R1L(low-order bitsof R1)

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