IR3522

Page 8

V3.01

Note 1: Guaranteed by design, but not tested in production

Note 2: VDACx Outputs are trimmed to compensate for Error & Amp Remote Sense Amp input offsets

Bold Letters: Critical specs

SYSTEM SET POINT TEST

Converter output voltage is determined by the system set point voltage which is the voltage that appears at the

FBx pins when the converter is in regulation. The set point voltage includes error terms for the VDAC digital-to-

analog converters, the Error Amp input offsets, and the Remote Sense input offsets. The voltage appearing at

the VDACx pins is not the system set point voltage. System set point voltage test circuits for Outputs 1 and 2 are

shown in Figures 2A and 2B.

CVREF1

RROSC

RVREF1

ROCSET1

EAOUT1

FB1

OC SET1

VREF1

VOSEN1-

VOSEN1+

VOUT1

LGND

ROSC

IR OSC

EAOUT

VOSNS-

VREF1

BUFFER

AMPLIFIER

ROSC BUFFER

AMPLIFIER

0.6V

"FAST"

VDAC

ISINK

ISOURCE

IR3522

SYSTEM

SET POINT

VOLTAGE

IOCSET1

CURRENT

SOURCE

GENERATOR

REMOTE SENSE

AMPLIFIER

ERROR

AMPLIFIER

IROSC

Figure 2A - Output 1 System Set Point Test Circuit

VREF_TRACK

FB2

EAOUT2

VOUT2

VOSEN2+

VOSEN2-

VOSNS-

EAOUT

SYSTEM

SET POINT

VOLTAGE

IR3522

ERROR

AMPLIFIER 2

REMOTE SENSE

AMPLIFIER 2

VOUT1

Figure 2B - Output 2 System Set Point Test Circuit

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

VCCL

Supply Current

3.5

7

15

mA

UVLO Start Threshold

4.20

4.43

4.7

V

UVLO Stop Threshold

3.8

3.99

4.3

V

Hysteresis

0.36

0.42

0.46

V