IR3522

Page 14

V3.01

Serial VID Control

The IR3522 outputs can be controlled via a serial VID Interface (SVID) which employs a Fast Mode I

VREF1, which is the reference for VOUT1, can also be programmed to boot-up to one of four codes through pins

VID0 and VID1 prior to ENABLE rising if SVID communication is not available prior to power-up. Refer to Table 4.

Pins VID0 and VID1 have internal 100K pull-up resistors to an internal 3.3V. The SVID controls both the VOUT1

and VOUT2 margining (see Table 2 or 3) depending on which serial address precedes the data string. See Table 1

for proper address codes. If the top address is used, then both outputs will coincide with the values in Table 2

depending on data code used, where VOUT2 is always half the value of VOUT1. The second address will only

have an effect on VOUT2’s amplitude (margining +26.67 % and -25 %) as defined in Table 3. Since there is no

internal compensation for Vref_track (VOUT2 reference), It is recommended that VOUT2 be incremented to its

final value to prevent possible output overshoot. If no serial command is received before an enable event (ENABLE

pin going high), the controller’s VOUT1 will startup in a default state as indicated in Table 4 and VOUT2 to 0.75 V

(half of VDAC).

Addresses and data are serially transmitted in 8-bit words. The first data bit of the SVID data word represents the

PSI_L bit and will be ignored by the IR3522 therefore this system will never enter a power-saving mode. The

remaining data bits SVID[6:0] select the desired VOUTx regulation voltage as defined in Table 2 or Table 3

depending address chosen. VOUT1 is divided in half by an internal resistor divider to provide a reference voltage

(Vref_track) for VOUT2. This allows VOUT2 to track VOUT1 maintaining a desired differential voltage. SVID [6:0]

are the inputs to the Digital-to-Analog Converter (VREF) which then provides an analog reference voltage to the

transconductance type buffer amplifier. This VREF buffer provides a system reference on the VREF1 pin. The

VREF1 voltage along with error amplifier and remote sense differential amplifier input offsets are post-package

trimmed to provide a 0.5% system set-point accuracy, as measured in Figures 2A and 2B. VREF1 slew rates are

programmable by properly selecting external series RC compensation networks located between the VREF1 and

the LGND pins. The VREF1 source and sink currents are derived off the external oscillator frequency setting

voltage throughout VID transitions resulting in a power supply input and output capacitor inrush currents, along with

output voltage overshoot, to be well controlled.

The ADDR1 and ADDR2 pins (5, 6) are reserved for controller addressing. These pins have internal 100K pull-up

resistors to an internal 3.3V. By floating or shorting to ground these two pins, four different controller identification

address states can be made. By setting bit 2 and 3 of the SVI address codes (see Figure 8) to the desired controller

address, a CPU can communicate with one controller while ignoring other controllers sharing the same SVID bus.

SVI Address [6:0] + Wr

6

5

4

ADDR1

ADDR2

1

0

WR

Figure 8 Bit 2 and 3 are use for Controller addressing

The SCL and SDA pins require external pull-up biasing and should not be floated. Biasing of pins SDA, SCL, VID0,

VID1, ADDR1 and ADDR2 prior to applying VCCL is acceptable. For Write, WR=0.

SVI Address

SVI Address [6:0] + Wr

Description

[bit6 :bit5 : bit4 : ADDR1 _ ADDR2 : bit1 : bit0 : WR]

1101_1100 in binary or D_C in hex if ADDR1 and ADDR2 pins are high

Set VID only Output 1

1101_1010 in binary or D_A in hex if ADDR1 and ADDR2 pins are high

Set VID only Output 2

BOLD indicates the pin states of ADDR1 and ADDR2, in this case high or floating.

Table 1 – SVI Address