IR3522

Page 17

V3.01

Tracking

Fault

VID_OFF

Response

Open

Daisy

Open

Sense

Open

Control

UVLO

(VCCL)

OC

Over

Voltage

Disable

SVID

UVLO

(Vout)

Latch

UVLO CLEARED Latch

ENABLE CLEARED Latch

SS Latch

No

Reset

Recycle VCCL

Recycle EN or Cycle VID_OFF through

SVID

SS discharge below

0.22V

No

Outputs

Affected

Both

none

Disables

EA

Yes

No

No

Soft Stop

No

Yes

No

CROWBAR

Yes

No

Flags

PGood

Yes

8

PHSOUT

No

250ns

Delays

32

Clock

Pulses

No

Pulses

No

Delay

Counter

No

Blanking

Time

No

No

Additional

Yes,

Flagged

Response

IIN1 pin is pulled-up to VCCL when SS discharge below 0.35V. This action latches on the Phase IC(s)

Diode Emulation Mode which insure proper current sharing during soft start**.

No

*Pulse number range depends on Rosc value selected (See Specifications Table)

** IIN1 is pulled low when SS charges above 0.4V.

Table 5 – IR3522 Fault protocol

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