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PCA9620 Datasheet(PDF) 51 Page - NXP Semiconductors |
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PCA9620 Datasheet(HTML) 51 Page - NXP Semiconductors |
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51 / 71 page ![]() PCA9620 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 — 9 December 2010 51 of 71 NXP Semiconductors PCA9620 Universal LCD driver for low multiplex rates 8.5 I2C-bus controller The PCA9620 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or transmit data to an I2C-bus master receiver. The only data output from PCA9620 are the acknowledge signals and the temperature readout byte of the selected device. 8.6 Input filters To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines. 8.7 I2C-bus slave address Device selection depends on the I2C-bus slave address. Four different I2C-bus slave addresses can be used to address the PCA9620 (see Table 32). The least significant bit of the slave address byte is bit R/W. Bit 1 and bit 2 of the slave address are defined by connecting the inputs A0 and A1 to either VSS (logic 0) or VDD (logic 1). Therefore, four instances of PCA9620 can be distinguished on the same I2C-bus. 8.8 I2C-bus protocol Table 32. I2C slave address Slave address Bit 7 6 5 4 3 2 1 0 MSB LSB slave address 0 1 1 1 0 A1 A0 R/W Fig 47. I2C-bus protocol write mode EXAMPLES a) transmit two bytes of RAM data 013aaa293 A 0 S 0 1110 0 control byte slave address RAM/command byte RAM DATA M S B L S B A A P R/W = 0 S 0 1110 0 0 1 A A A P RAM DATA A b) transmit two command bytes COMMAND S 0 1110 0 1 0 A A A P COMMAND A A c) transmit one command byte and two RAM date bytes COMMAND S 0 1110 0 1 0 00 01 A A A P RAM DATA A RAM DATA A A C O R S A 1 A 0 A 1 A 0 A 1 A 0 A 1 |
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