1.

General description

The PCK942P is a 1 : 18 low voltage clock distribution chip with 2.5 V or 3.3 V LVCMOS

output capabilities. The device is offered in two versions: the PCK942C has an LVCMOS

input clock, while the PCK942P has a LVPECL input clock. The 18 outputs are 2.5 V or

3.3 V LVCMOS compatible and feature the drive strength to drive 50

Ω series-terminated

transmission lines. With output-to-output skews of 200 ps, the PCK942P is ideal as a

clock distribution chip for the most demanding of synchronous systems. The 2.5 V output

also makes the device ideal for supplying clocks for a higher performance Pentium II

microprocessor-based design.

With a low output impedance of approximately 12

Ω, in both the HIGH and LOW logic

states, the output buffers of the PCK942P are ideal for driving series-terminated

transmission lines. With an output impedance of 12

Ω, the PCK942P can drive two

series-terminated transmission lines from each output. This capability gives the PCK942P

an effective fan-out of 1 : 36. The PCK942P provides enough copies of low skew clocks

for most high performance synchronous systems.

The differential LVPECL inputs of the PCK942P allow the device to interface directly with a

LVPECL fan-out buffer like the MC100EP111 to build very wide clock fan-out trees or to

couple to a high frequency clock source. The OE pin will place the outputs to a

high-impedance state. The OE pin has an internal pull-up resistor.

The 32-lead LQFP package was chosen to optimize performance, board space, and cost

of the device. The 32-lead LQFP package has a 7 mm

× 7 mm body size with a

conservative 0.8 mm pin spacing.

2.

Features

PCK942P

Low voltage 1 : 18 clock distribution chip

Rev. 01 — 17 February 2006

Product data sheet