AD9571 datasheet(16/20 Pages) AD

16 / 20 page

AD9571

Rev. 0 | Page 16 of 20

The value of the resistor is dependent on the board design and

timing requirements (typically 10 Ω to 100 Ω is used). CMOS

outputs are limited in terms of the capacitive load or trace

length that they can drive. Typically, trace lengths less than

6 inches are recommended to preserve signal rise/fall times

and signal integrity.

Ω

MICROSTRIP

GND

5pF

60.4

Ω

1.0 INCH

CMOS

Figure 15. Series Termination of CMOS Output

Termination at the far end of the PCB trace is a second option.

The CMOS outputs of the AD9571 do not supply enough current

to provide a full voltage swing with a low impedance resistive,

far-end termination, as shown in Figure 16. The far-end termin-

ation network should match the PCB trace impedance and

provide the desired switching point. The reduced signal swing

may still meet receiver input requirements in some applications.

This can be useful when driving long trace lengths on less

critical nets.

Ω

VPULLUP = 3.3V

CMOS

5pF

100

Ω

100

Ω

Figure 16. CMOS Output with Far-End Termination

LVPECL CLOCK DISTRIBUTION

The low voltage, positive emitter-coupled logic (LVPECL)

outputs of the AD9571 provide the lowest jitter clock signals

available from the AD9571. The LVPECL outputs (because they

are open emitter) require a dc termination to bias the output

transistors. The simplified equivalent circuit in Figure 13 shows

the LVPECL output stage.

In most applications, a standard LVPECL far-end termination is

recommended, as shown in Figure 17. The resistor network is

designed to match the transmission line impedance (50Ω) and

the desired switching threshold (1.3 V).

3.3V

LVPECL

Ω

SINGLE-ENDED

(NOT COUPLED)

3.3V

LVPECL

127

Ω

127

Ω

VT = VCC – 1.3V

Figure 17. LVPECL Far-End Termination

3.3V

LVPECL

DIFFERENTIAL

(COUPLED)

3.3V

LVPECL

100

Ω

0.1nF

200

Ω

200

Ω

Figure 18. LVPECL with Parallel Transmission Line

LVDS CLOCK DISTRIBUTION

Low voltage differential signaling (LVDS) is a second differ-

ential output option for the AD9571. LVDS uses a current mode

output stage with a factory programmed current level. The

normal value (default) for this current is 3.5 mA, which yields a

350 mV output swing across a 100 Ω resistor. The LVDS

outputs meet or exceed all ANSI/TIA/EIA-644 specifications.

A recommended termination circuit for the LVDS outputs is

shown in Figure 19.

Ω

LVDS

100

Ω

Figure 19. LVDS Output Termination

See the AN-586 Application Note on the Analog Devices

website at www.analog.com for more information about LVDS.

REFERENCE INPUT

By default, the crystal oscillator is enabled and used as the

reference source, which requires the connection of an external

25 MHz crystal. The REFSEL pin is pulled high internally by

about 30 kΩ to support default operation. When REFSEL is tied

low, the crystal oscillator is powered down, and the REFCLK pin

must provide a good quality 25 MHz reference clock instead.

This single-ended input can be driven by either a dc-coupled

LVCMOS level signal or an ac-coupled sine wave or square

wave, provided that an external divider is used to bias the input

at VS/2.

Table 17. REFSEL Definition

REFSEL

Reference Source

REFCLK input

Internal crystal oscillator

POWER AND GROUNDING CONSIDERATIONS AND

POWER SUPPLY REJECTION

Many applications seek high speed and performance under

less than ideal operating conditions. In these application

circuits, the implementation and construction of the PCB is as

important as the circuit design. Proper RF techniques must be

used for device selection, placement, and routing, as well as for

power supply bypassing and grounding to ensure optimum

performance.

AD9571 Datasheet(PDF) 16 Page - Analog Devices

AD9571 Datasheet(HTML) 16 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Datasheet Download

Link URL