Data Sheet

9

Rev. 1.0, 2008-09-30

TLE4675

General Product Characteristics

4.3

Thermal Resistance

Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go

to www.jedec.org.

Pos.

Parameter

Symbol

Limit Values

Unit

Conditions

Min.

Typ.

Max.

TLE4675D Package PG-TO252-5

4.3.1

Junction to Case

R

thJC

–3.7

–K/W

1)

1) Not subject to production test, specified by design

4.3.2

Junction to Ambient

R

thJA

–

110

–

K/W

Footprint only 1)2)

2) Specified

R

(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 x 70µm Cu).

4.3.3

–

57

–

K/W

area on PCB 1)2)

4.3.4

–

42

–

K/W

area on PCB 1)2)

4.3.5

–

27

–

K/W

2s2p PCB 1)3)

3) Specified

R

(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).

Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.

TLE4675G Package PG-TO263-5

4.3.6

Junction to Case

R

thJC

–3.7

–K/W

1)

4.3.7

Junction to Ambient

R

thJA

–

123

–

K/W

Footprint only 1)2)

4.3.8

–

42

–

K/W

heatsink area 1)2)

4.3.9

–

33

–

K/W

heatsink area 1)2)

4.3.10

–

22

–

K/W

2s2p PCB 1)3)