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TLE8110EE Datasheet(PDF) 61 Page - Infineon Technologies AG

Part # TLE8110EE
Description  Smart Multichannel Low Side Switch with Parallel Control and SPI Interface
PDF  72 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

TLE8110EE Datasheet(HTML) 61 Page - Infineon Technologies AG

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Data Sheet
61
Rev. 1.0, 2009-06-15
FLEX
Smart Multi-Channel Switch
Control of the device
S_SI
SPI_Serial Input
DCC
11
10
987
6543
210
DRA
010
10000
0000
DRB
011
00000
0000
DRACL
000
10000
0000
DRBCL
001
00000
0000
DMSCL/OPSx
1
0
0
0
OPSx
DMS1/OPSx
1
0
1
1
OPSx
DMS2/OPSx
1
1
0
1
OPSx
DMS3/OPSx
1
1
1
0
OPSx
DMSx/OPS1
1
DMSx
0000
0001
DMSx/OPS2
1
DMSx
0000
0010
DMSx/OPS3
1
DMSx
0000
0100
DMSx/OPS4
1
DMSx
0000
1000
DMSx/OPS5
1
DMSx
0001
0000
DMSx/OPS6
1
DMSx
0010
0000
DMSx/OPS7
1
DMSx
0100
0000
DMSx/OPS8
1
DMSx
1000
0000
Field
Bits
Type
Description
DCC_DRA
11:0
W
DRA - Diagnosis Register A (see Chapter 12.3.2.1)
Read out Diagnosis Register A. Return the contents in the next SPI
Frame. (see Chapter 12.3.2.2)
DCC_DRB
11:0
W
DRB - Diagnosis Register B (see Chapter 12.3.2.1)
Read out Diagnosis Register B. Return the contents in the next SPI
Frame. (see Chapter 12.3.2.2)
DCC_
DRACL
11:0
W
DRACL - Diagnosis Register A Clear
Clear the contents of the Diagnosis Register A. Return the cleared
contents in the next SPI Frame. If the Diagnosis Error Remains,
the Information remains.(see Chapter 12.3.2.2)
DCC_
DRBCL
11:0
W
DRBCL - Diagnosis Register B Clear
Clear the contents of the Diagnosis Register B. Return the cleared
contents in the next SPI Frame. If the Diagnosis Error Remains,
the Information remains. (see Chapter 12.3.2.2)
DCC_
DMSCL
11:8
W
DMSCL/OPSx - Diagnosis Mode Set, Clear / Output Pins Set
On sending this command, the diagnosis registers DRA, DRB as well
as the “virtual” Diagnosis Output Registers DO[7:0] (see
Chapter 12.3.2.3) are cleared. Output Pin Settings are done
according the content of OPSx.
Returns the contents of cleared DR2 on SO in the 2nd byte of the
actual communication frame and the Output Pin Feedback in
the 1st Byte of the next frame. (see Chapter 12.3.2.3)



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