DVSR CODEC

14

MX802

1998 MX-COM, Inc.

www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054

Doc. # 20480033.008

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA

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4.3

Encoder and Decoder Control : Analog Input and Output Control

The Control Register, Byte 0: bits 0 to 5, are used together with the codec Powersave Bit (Byte 1: bit 3) to

control codec input/output conditions and sample rates. Figure 3 shows the codec functional situation.

200 k

(nom)

500 k

(nom)

INPUT

BIAS

OUTPUT

BIAS

AUDIO

BYPASS

V

BIAS

V

BIAS

CVSD CODEC

MOD

DEMOD

AUDIO IN

AUDIO OUT

Figure 3: Analog Control (with reference to Figure 1)

Control Register

Circuit Switches

Codec

Powersave

Bit

Decoder

Control

Audio

Bypass

Audio

Out

Output

Bias

OFF = Switch Open

ON = Switch ON

Note

0

0

0

0

0

0

0

0

1

0

1

0

OFF

ON

OFF

ON

OFF

OFF

OFF

OFF

OFF

Decoder idling fed with

“1010101…” pattern at

32kbps.

1

0

–

0

0

–

1

1

–

1

1

–

1

OFF

–

OFF

ON

–

ON

OFF

–

OFF

Decoder running at the

selected sampling rate.

1

1

1

1

1

–

1

0

0

0

0

–

1

0

0

1

1

–

1

0

1

0

1

–

1

OFF

ON

OFF

OFF

-

OFF

OFF

OFF

OFF

OFF

–

OFF

ON

OFF

ON

ON

-

ON

Decoder circuits

powersaved.

Encoder

Control

Input

Bias

2

0

0

0

0

0

0

0

0

1

0

1

0

ON

OFF

OFF

Encoder running at 32kbps

but Encoder Data O/P forced

to idle pattern “01010…”

0

-

0

0

–

1

1

–

1

1

–

1

OFF

–

OFF

Encoder running at selected

sampling rate

1

-

1

0

-

1

0

-

1

0

-

1

ON

-

ON

Encoder circuits powersaved.

Table 7: Analog Control (with reference to Figure 3)

Notes

1. If the Delta Codec is in the Direct Access mode, these sampling rates will be as provided by the externally

applied clock.

2.

The input bias switch is operated by the Control Register Codec Powersave and Encoder Control bits to

codec is powersaved, or the encoder control bits are set to 0, so that input bias can be established

quickly prior to operation.