TAS5717 datasheet(6/67 Pages) TI

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TAS5717

TAS5719

SLOS655A

– NOVEMBER 2010 – REVISED FEBRUARY 2011

www.ti.com

PIN FUNCTIONS (continued)

5-V

TYPE(1)

TERMINATION(2)

DESCRIPTION

TOLERANT

NAME

NO.

GVDD_OUT

Gate drive internal regulator output

HPL_IN

Headphone left IN (single-ended, analog IN)

HPL_OUT

Headphone left OUT (single-ended, analog OUT)

HP_PWML

PWM left-channel headphone out

HP_PWMR

PWM right-channel headphone out

HPR_IN

Headphone right IN (single-ended, analog IN)

HPR_OUT

Headphone right OUT (single-ended, analog OUT)

HP_SD

Headphone shutdown (active-low)

HPVDD

Headphone supply

HPVSS

Headphone ground

LRCLK

5-V

Pulldown

Input serial audio data left/right clock (sample rate clock)

MCLK

5-V

Pulldown

Master clock input

OSC_RES

Oscillator trim resistor. Connect an 18-k

Ω 1% resistor to DVSSO.

OUT_A

Output, half-bridge A

OUT_B

Output, half-bridge B

OUT_C

Output, half-bridge C

OUT_D

Output, half-bridge D

PDN

5-V

Pullup

Power down, active-low. PDN prepares the device for loss of power

supplies by shutting down the noise shaper and initiating the PWM

stop sequence.

PGND_AB

Power ground for half-bridges A and B

PGND_CD

Power ground for half-bridges C and D

PLL_FLTM

PLL negative loop-filter terminal

PLL_FLTP

PLL positive loop-filter terminal

PVDD_AB

Power-supply input for half-bridge output A

PVDD_CD

Power-supply input for half-bridge output C

RESET

5-V

Pullup

Reset, active-low. A system reset is generated by applying a logic low

to this pin. RESET is an asynchronous control signal that restores the

DAP to its default conditions, and places the PWM in the hard-mute

(high-impedance) state.

SCL

5-V

I2C serial control clock input

SCLK

5-V

Pulldown

Serial audio data clock (shift clock). SCLK is the serial audio port input

data bit clock.

SDA

DIO

5-V

I2C serial control data interface input/output

SDIN

5-V

Pulldown

Serial audio data input. SDIN supports three discrete (stereo) data

formats.

SSTIMER

Controls ramp time of OUT_X to minimize pop. Leave this pin floating

for BD mode. Requires capacitor of 2.2 nF to GND in AD mode. The

capacitor determines the ramp time.

STEST

Factory test pin. Connect directly to DVSS.

VR_ANA

Internally regulated 1.8-V analog supply voltage. This pin must not be

used to power external devices.

VR_DIG

Internally regulated 1.8-V digital supply voltage. This pin must not be

used to power external devices.

VREG

Digital regulator output. Not to be used for powering external circuitry.

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