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TAS5717 Datasheet(PDF) 22 Page - Texas Instruments |
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TAS5717 Datasheet(HTML) 22 Page - Texas Instruments |
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22 / 67 page ![]() 23 22 SCLK 32Clks LRCLK(NoteReversedPhase) LeftChannel 24-BitMode 1 19 18 20-BitMode 16-BitMode 15 14 MSB LSB 32Clks RightChannel 2-ChannelI S(PhilipsFormat)StereoInput 2 T0034-01 5 4 9 8 1 0 0 4 5 1 0 23 22 1 19 18 15 14 MSB LSB 5 4 9 8 1 0 0 4 5 1 0 SCLK TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com SERIAL INTERFACE CONTROL AND TIMING I2S Timing I2S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 32, 48, or 64 × fS is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes state to the first bit of data on the data lines. The data is written MSB-first and is valid on the rising edge of bit clock. The DAP masks unused trailing data-bit positions. NOTE: All data presented in 2s-complement form with MSB first. Figure 26. I2S 64-fS Format 22 Submit Documentation Feedback © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): TAS5717 TAS5719 |
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