FM25Q32 datasheet(22/61 Pages) FIDELIX

22 / 61 page

preliminary(Aug.18.2010)

FM25Q32

11.2.8 Write Status Register (01h)

The Write Status Register instruction allows the Status Register to be written. A Write Enable

instruction must previously have been executed for the device to accept the Write Status Register

Instruction (Status Register bit WEL must equal 1). Once write is enabled, the instruction is entered

by driving /CS low, sending the instruction code “01h”, and then writing the status register data byte

or word as illustrated in figure 8. The Status Register bits are shown in figure 3 and described

earlier in this datasheet.

Only non-volatile Status Register bits SRP0, SEC, TB, BP2, BP1, BP0 (bits 7, 5, 4, 3, 2 of Status

The /CS pin must be driven high after the eighth or sixteenth bit of data that is clocked in. If this is

not done the Write Status Register instruction will not be executed. If /CS is driven high after the

eighth clock, the QE and SRP1 bits will be

cleared to 0. After /CS is driven high, the self-timed

Write Status Register cycle will commence for a time duration of tw (See AC Characteristics). While

the Write Status Register cycle is in progress, the Read Status Register instruction may still be

accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status Register

cycle and a 0 when the cycle is finished and ready to accept other instructions again. After the

Write Status Register cycle has finished, The Write Enable Latch (WEL) bit in Status Register will

be cleared to 0.

The Write Status Register instruction allows the Block Protect bits (SEC, TB, BP2, BP1 and BP0)

to be set for protecting all, a portion, or none of the memory from erase and program instructions.

Protected areas become read-only (see Status Register Memory Protection table and description).

The Write Status Register instruction also allows the Status Register Protect bits (SRP0, SRP1) to

be set. Those bits are used in conjunction with the Write protect (/WP) pin, Lock out or OTP

features to disable writes to the status register. Please refer to 11.1.16 for detailed descriptions

Status Register protection methods. Factory default all Status Register bits are 0.

/CS

CLK Mode 0

Mode 3

Instruction (01h)

High Impedance

11 12

13 14 15 16

17 18 19 20 21 22

Mode 0

Mode 3

Status Register1 In

=MSB

Status Register2 In

Figure 8. Write Status Register Instruction Sequence Diagram

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