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FM25Q32 Datasheet(PDF) 29 Page - FIDELIX

Part # FM25Q32
Description  32M-BIT Serial Flash Memory with 4KB Sectors, Dual and Quad I/O SPI
PDF  61 Pages
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Manufacturer  FIDELIX [FIDELIX]
Direct Link  http://www.fidelix.co.kr
Logo FIDELIX - FIDELIX

FM25Q32 Datasheet(HTML) 29 Page - FIDELIX

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preliminary(Aug.18.2010)
29
FM25Q32
11.2.13 Page Program (02h)
The Page Program instruction allows from one byte to 256 bytes (a page) of data to be
programmed at previously erased (FFh) memory locations. A Write Enable instruction must be
executed before the device will accept the Page Program Instruction (Status Register bit WEL= 1).
The instruction is initiated by driving the /CS pin low and then shifting the instruction code “02h”
followed by a 24-bits address (A23-A0) and at least one data byte, into the DI pin. The /CS pin
must be held low for the entire length of the instruction while data is being sent to the device. The
Page Program instruction sequence is shown is figure 13.
If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant
address bits) should be set to 0. If the last address byte is not zero, and the number of clocks
exceeds the remaining page length, the addressing will wrap to the beginning of the page. In some
cases, less than 256 bytes (a partial page) can be programmed without having any effect on other
bytes within the same page. One condition to perform a partial page program is that the number of
clocks can not exceed the remaining page length. If more than 256 bytes are sent to the device the
addressing will wrap to the beginning of the page and overwrite previously sent data.
As with the write and erase instructions, the /CS pin must be driven high after the eighth bit of the
last byte has been latched. If this is not done the Page Program instruction will not be executed.
After /CS is driven high, the self-timed Page Program instruction will commence for a time duration
of tPP (See AC Characteristics). While the Page Program cycle is in progress, the Read Status
Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is
a 1 during the Page Program cycle and becomes a 0 when the cycle is finished and the device is
ready to accept other instructions again. After the Page Program cycle has finished and Write
Enable Latch (WEL) bit in the Status Register is cleared to 0. The Page Program instruction will not
be executed if the addressed page is protected by the Block Protect (SEC, TB, BP2, BP1, and
BP0) bits,
0
1
2
3
4
5
6
7
Instruction (02h)
/CS
CLK
Mode 3
Mode 0
DI
8
9
10
24 -Bit Address
31
30
29
28
23
3
2
1
0
22
21
33
32
35
34
37
36
39
38
7
6
5
4
3
2
1
0
Data Byte 1
*
*
/CS
CLK
Mode 3
Mode 0
DI
50
54
53
52
51
55
7
6
5
4
3
2
1
0
Data Byte 256
40
44
43
42
41
46
45
47
49
48
Data Byte 3
Data Byte 2
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
= MSB
*
0
1
2
3
4
5
6
7
Instruction (02h)
/CS
CLK
Mode 3
Mode 0
DI
8
9
10
24 -Bit Address
31
30
29
28
23
3
2
1
0
22
21
33
32
35
34
37
36
39
38
7
6
0
1
2
3
4
5
6
7
Instruction (02h)
/CS
CLK
Mode 3
Mode 0
DI
8
9
10
24 -Bit Address
31
30
29
28
23
3
2
1
0
22
21
33
32
35
34
37
36
39
38
7
6
5
4
3
2
1
0
Data Byte 1
*
*
/CS
CLK
Mode 3
Mode 0
DI
50
54
53
52
51
55
7
6
5
4
3
2
1
0
Data Byte 256
40
5
4
3
2
1
0
Data Byte 1
*
*
/CS
CLK
Mode 3
Mode 0
DI
50
54
53
52
51
55
7
6
5
4
3
2
1
0
Data Byte 256
40
44
43
42
41
46
45
47
49
48
Data Byte 3
Data Byte 2
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
= MSB
*
Figure 13. Page Program Instruction Sequence Diagram



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