PCA9525

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Product data sheet

Rev. 1 — 25 February 2011

4 of 22

NXP Semiconductors

PCA9525

Simple 2-wire bus buffer

clocking when communicating with them. The buffer includes hysteresis to ensure clean

switching signals are output, especially with slow rise times on high capacitively loaded

buses. Output ports are open-drain type and require external pull-up resistors.

7.3 SDA_IN, SDA_OUT — data signal inputs/outputs

The data signal buffer is bidirectional. The port (SDA_IN, SDA_OUT) which first falls

coming from the opposite side. As the ‘input’ signal continues to fall, it will then drive the

‘output’ side LOW. Again, hysteresis is applied to the buffer to minimize the effects of

noise.

At some points during the communication, the data direction will reverse, e.g., when the

slave transmits an acknowledge (ACK), or responds with its register contents. During

these times, the controlling ‘input’ side will have to rise back above the unlock voltage

and pull (what was) the ‘input’ side LOW again. This will cause a ‘pulse’ on the ‘input’ side,

which can be quite a long duration in high capacitance buses. However, this pulse will not

interfere with the actual data transmission, as it should not occur during times of clock line

requirements are still met. Ports are open-drain type and require external pull-up resistors.

7.4 Enable (EN) — activate buffer operations

The active HIGH enable input (EN) can be used to disable the buffer, for the purpose of

isolating sections of the bus. The IC should only be disabled when the bus is idle. This

prevents truncation of commands which may confuse other devices on the bus. Enable

(EN) may also be used to progressively activate sections of the bus during system

start-up. Bus sections slow to respond on power-up can be kept isolated from the main

system to avoid interference and collisions. The pin must be externally driven to a valid

state.

7.5 Direction (DIR) — clock buffer direction control

The direction input (DIR) is used to change the signal direction of the SCL ports. When the

DIR pin is logic LOW, the clock signal input is SCL_IN and the buffered output is

SCL_OUT. When the DIR pin is logic HIGH, the clock signal input is SCL_OUT and the

buffered output is SCL_IN. The pin must be externally driven to a valid state.