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ZXLD1350 Datasheet(PDF) 15 Page - Diodes Incorporated |
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ZXLD1350 Datasheet(HTML) 15 Page - Diodes Incorporated |
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15 / 22 page ![]() ZXLD1350 ZXLD1350 Document number: DS33468 Rev. 7 - 2 15 of 22 www.diodes.com November 2010 © Diodes Incorporated A Product Line of Diodes Incorporated Application Information (Continued) High frequency PWM mode At PWM frequencies above 10kHz and for duty cycles above 0.16, the output of the internal low pass filter will contain a DC component that is always above the shutdown threshold. This will maintain continuous device operation and the nominal average output current will be proportional to the average voltage at the output of the filter, which is directly proportional to the duty cycle. (See Figure 3 – High frequency PWM operating waveforms). For best results, the PWM frequency should be maintained above the minimum specified value of 10kHz, in order to minimize ripple at the output of the filter. The shutdown comparator has approximately 50mV of hysteresis, to minimize erratic switching due to this ripple. An upper PWM frequency limit of approximately one tenth of the operating frequency is recommended, to avoid excessive output modulation and to avoid injecting excessive noise into the internal reference. Figure 3. High Frequency PWM operating waveforms The nominal average value of output current in this mode is given by: IOUTnom »0.1DPWM/RS for DPWM >0.16 This mode will give minimum output ripple and reduced radiated emission, but with a reduced dimming range (approx.5:1). The restricted dimming range is a result of the device being turned off when the DC component on the filter output falls below 200mV. Shutdown mode Taking the ADJ pin to a voltage below 0.2V for more than approximately 100 μs, will turn off the output and supply current will fall to a low standby level of 15 μA nominal. Note that the ADJ pin is not a logic input. Taking the ADJ pin to a voltage above VREF will increase output current above the 100% nominal average value. (See graphs for details). |
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