No. 4796-13/13

LC72321

This catalog provides information as of December, 1997. Specifications and information herein are subject to

change without notice.

s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace

equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of

which may directly or indirectly cause injury, death or property loss.

s Anyone purchasing any products described or contained herein for an above-mentioned use shall:

ΠAccept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and

distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all

damages, cost and expenses associated with such use:

 Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on

SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees

jointly or severally.

s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for

volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied

regarding its use or any infringements of intellectual property rights or other rights of third parties.

Continued from preceding page.

Mnemonic

Operand

Function

Operation

Machine code

1st

2nd

D15 14 13 12 11 10 9 8

7 6 5 4

3 2 1 D0

LCD

M

I

Output segment pattern

LCD (DIGIT)

← M

1

1

1

0

0

0

DH

DL

DIGIT

to LCD digit direct

LCP

M

I

Output segment pattern

LCD (DIGIT)

← PLA ← M

1

1

1

0

0

1

DH

DL

DIGIT

to LCD digit through PLA

IN

M

P

Input port data to M

M

← (Port (P))

1

1

1

0

1

0

DH

DL

P

OUT

M

P

Output contents of M to port

(Port (P))

← M

1

1

1

0

1

1

DH

DL

P

SPB

P

N

Set port bits

(Port (P)) N

← 1

1

1

1

1

0

0

0 0

P

N

RPB

P

N

Reset port bits

(Port (P)) N

← 0

1

1

1

1

0

1

0 1

P

N

Test port bits,

if (Port (P)) N = all 1s,

TPT

P

N

then skip if all bits

then skip

1

1

1

1

1

0

1 0

P

N

specified are true

Test port bits,

if (Port (P)) N = all 0s,

TPF

P

N

then skip if all bits

then skip

1

1

1

1

1

1

1 1

P

N

specified are false

UCS

I

Set I to UCCW1

UCCW1

← I

0

0

0

0

0

0

0 1

0 0 0 0

I

UCC

I

Set I to UCCW2

UCCW2

← I

0

0

0

0

0

0

1 1

0 0 0 0

I

FPC

N

F port I/O control

FPC latch

← N

0

0

0

1

0

0

0 0

0 0 0 0

N

CKSTP

Clock stop

Stop clock if HOLD = 0

0

0

0

1

0

0

0 1

0 0 0 0

0 0 0

0

DAC

I

Load M to D/A registers

DAreg

← DAC DATA

0

0

0

0

0

0

1 0

0 0 0 0

I

SIO

I1

I2

Serial I/O control

SIOCW

← I1, I2

0

0

0

1

0

0

1 1

I1

I2

SIOL

M

I

Load SIOreg to M

M

← SIOreg

0

0

0

1

1

0

DH

DL

I

SIOS

M

I

Store M to SIOreg

SIOreg

← M

0

0

0

1

0

1

DH

DL

I

BEEP

I

Beep control

BEEPreg

← I

0

0

0

1

0

0

1 0

0 0 0 0

I

NOP

No operation

0

0

0

0

0

0

0 0

0 0 0 0

0 0 0

0