No. 5544-14/14

LC72P366

This catalog provides information as of November, 1996. Specifications and information herein are subject to

change without notice.

s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace

equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of

which may directly or indirectly cause injury, death or property loss.

s Anyone purchasing any products described or contained herein for an above-mentioned use shall:

distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all

damages, cost and expenses associated with such use:

SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees

jointly or severally.

s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for

volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied

regarding its use or any infringements of intellectual property rights or other rights of third parties.

Continued from preceding page.

Mnemonic

Operand

Function

Operation

Machine code

1st

2n

D15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

D0

SIO

I1

I2

Serial I/O control

SIO reg

← I1,I2

0

0

0

0

0

0

0

1

I1

I2

UCS

I

Set I to UCCW1

UCCW1

← I

0

0

0

0

0

0

0

0

0

0

0

1

I

UCC

I

Set I to UCCW2

UCCW2

← I

0

0

0

0

0

0

0

0

0

0

1

0

I

BEEP

I

Beep control

BEEP reg

← I

0

0

0

0

0

0

0

0

0

1

1

0

I

DZC

I

Dead zone control

DZC reg

← I

0

0

0

0

0

0

0

0

1

0

1

1

I

TMS

N

Set timer register

Timer reg

← I

0

0

0

0

0

0

0

0

1

1

0

0

N

IOS

PWn

N

Set port control word

IOS reg PWn

← N

1

1

1

1

1

1

1

0

PWn

N

IN

M

Pn

Input port data to M

M

← (Pn)

1

1

1

0

1

0

Pn

OUT

M

Pn

Output contents of M

Pn

← M

1

1

1

0

1

1

Pn

to port

SPB

Pn

N

Set port bits

(Pn) N

← 1

0

0

0

0

0

0

1

0

Pn

N

RPB

Pn

N

Reset port bits

(Pn) N

← 0

0

0

0

0

0

0

1

1

Pn

N

TPT

Pn

N

Test port bit, then skip

if (Pn) N = all “1”,

1

1

1

1

1

1

0

0

Pn

N

if all bits specified are

then skip

true

TPF

Pn

N

Test port bits, then skip

if (Pn) N = all “0”,

1

1

1

1

1

1

0

1

Pn

N

if all bits specified are

then skip

false

BANK

I

Select Bank

BANK

← I

0

0

0

0

0

0

0

0

0

1

1

1

I

HALT

I

Halt mode control

HALT reg

← I,

0

0

0

0

0

0

0

0

0

1

0

0

I

then CPU click stop

CKSTP

Clock stop

stop X’tal OSC if

0

0

0

0

0

0

0

0

0

1

0

1

HOLD = 0

NOP

No operation

No operation

0

0

0

0

0

0

0

0

0

0

0

0