MAX9268 datasheet(27/35 Pages) MAXIM

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Gigabit Multimedia Serial Link Deserializer

with LVDS System Interface

______________________________________________________________________________________ 27

ERR Output

The MAX9268 has an open-drain ERR output. This

output asserts low whenever the number of decoding errors

exceeds the error threshold ERRTHR (0x0C) during normal

operation, or when at least one PRBS error is detected dur-

ing the PRBS test. ERR reasserts high whenever DECERR

(0x0D) resets due to DECERR readout, video link lock, or

autoerror reset.

Autoerror Reset

The default method to reset errors is to read the

respective error registers in the MAX9268 (0x0D, 0x0E).

Autoerror reset clears the decoding error counter DECERR

and the ERR output ~1Fs after ERR goes low. Autoerror

reset is disabled on power-up. Enable autoerror reset

through AUTORST (0x06 D6). Autoerror reset does not

run when the device is in PRBS test mode.

Self-PRBS Test

The GMSL serializer/MAX9268 link includes a PRBS pattern

generator and bit-error verification function. Set PRBSEN

= 1 (0x04 D5) first in the GMSL serializer and then the

MAX9268 to start the PRBS test. Set PRBSEN = 0 (0x04 D5)

first in the MAX9268 and then the GMSL serializer to exit the

PRBS self-test. The MAX9268 uses an 8-bit register (0x0E)

to count the number of detected errors. The control link

also controls the start and stop of the error counting. During

PRBS mode, the device does not count decoding errors

and the MAX9268 ERR output reflects PRBS errors only.

Microcontrollers on Both Sides of the

GMSL Link (Dual µC Control)

Usually a single FC is used for GMSL device programming

and control-channel communications and is located either

on the serializer side for video-display applications or on

the deserializer (MAX9268) side for image-sensing appli-

cations. In the former case, the CDS pins of the serializer/

deserializer are set to low; in the latter case, they are set to

high. However, if the CDS pin of the serializer is low and the

same pin on the deserializer is high, then FCs connected

at each device are enabled as masters simultaneously. In

such a case, the FC on either side communicates with the

GMSL serializer and the MAX9268.

Contention can occur if the FCs attempt to use the control

channel at the same time. The serializer/deserializer do

not in themselves provide a way to avoid contention. The

fact that an acknowledge is not received when contention

occurs can be used to trigger a retry. Alternatively, a higher

layer protocol can be implemented to avoid contention. In

addition, if UART communication across the serial link is

not required, the FCs can disable the forward and reverse

control channel through the REVCCEN and FWDCCEN

bits (0x04 D[1:0]) in the GMSL serializer/MAX9268. UART

communication across the serial link is prevented and

therefore contention between FCs can no longer occur.

During dual FC operation, if one of the CDS pins on either

side changes state, the link resumes the corresponding

state described in the Link Startup Procedure section.

As an example of dual FC use in an image-sensing appli-

cation, the GMSL serializer can be in sleep mode and

waiting for wake-up by the MAX9268. After wake-up, the

serializer-side FC sets the GMSL serializer’s CDS pin low

and assumes master control of the serializer’s registers.

Changing the Clock Frequency

Both the video clock rate (fTXCLKOUT_) and the control-

channel clock rate (fUART) can be changed on-the-fly

to support applications with multiple clock speeds. It is

recommended to enable the serial link after the video clock

stabilizes. Stop the video clock for 5Fs and restart the serial

link, or toggle SEREN after each change in the video clock

frequency, to recalibrate any automatic settings if a smooth

frequency change cannot be guaranteed. The reverse

control channel remains unavailable for 350Fs after serial

link start or stop. Limit on-the-fly changes in fUART to factors

of less than 3.5 at a time to ensure that the device recog-

nizes the UART sync pattern. For example, when lowering

the UART frequency from 1Mbps to 100kbps, first send

data at 333kbps and then at 100kbps to have reduction

ratios of 3 and 3.333, respectively.

LOCK Output Loopback

For quick loss-of-lock notification, the MAX9268 can loop

back its LOCK output to the GMSL serializer using the

INT signal. Connect the LOCK output to the INT input of

the MAX9268. The interrupt output on the GMSL serializer

follows the transitions at the LOCK output. Reverse control-

channel communication does not require an active forward

link to operate and accurately tracks the LOCK status of the

video link. LOCK asserts for video link only and not for the

configuration link.

GPIOs

The MAX9268 has two open-drain GPIOs available.

GPIO1OUT and GPIO0OUT (0x06 D3, D1) set the output

state of the GPIOs. The GPIO input buffers are always

enabled. The input states are stored in GPIO1 and GPIO0

(0x06 D2, D0). SET GPIO1OUT/GPIO0OUT to 1 when

using GPIO1/GPIO0 as an input.

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