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MAX9268 Datasheet(PDF) 5 Page - Maxim Integrated Products

Part # MAX9268
Description  Gigabit Multimedia Serial Link Deserializer with LVDS System Interface
PDF  35 Pages
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX9268 Datasheet(HTML) 5 Page - Maxim Integrated Products

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Gigabit Multimedia Serial Link Deserializer
with LVDS System Interface
_______________________________________________________________________________________ 5
AC ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100Ω Q1% (differential), TA = -40NC to +105NC, unless otherwise noted.
Typical values are at VAVDD = VDVDD = VIOVDD = 3.3V, TA = +25NC.)
Note 2: Minimum IIN due to voltage drop across the internal pullup resistor.
Note 3: Measured in serial link bit times. Bit time = 1/(30 x fTXCLKOUT_) for BWS = GND. Bit time = 1/(40 x fTXCLKOUT_) for VBWS =
VIOVDD.
Note 4: Rising to rising-edge jitter can be twice as large.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LVDS Output Pulse Position
tPPOSN
N = 0 to 6, tCLK =
1/fTXCLKOUT_,
fTXCLKOUT_ =
104MHz
(Figure 7)
fTXCLKOUT_ = 12.5MHz
N/7 x tCLK
- 250
N/7 x
tCLK
N/7 x tCLK
+ 250
ps
fTXCLKOUT_ = 33MHz
N/7 x tCLK
- 200
N/7 x
tCLK
N/7 x tCLK
+ 200
fTXCLKOUT_ = 78MHz
N/7 x tCLK
- 125
N/7 x
tCLK
N/7 x tCLK
+ 125
fTXCLKOUT_ = 104MHz
N/7 x tCLK
- 100
N/7 x
tCLK
N/7 x tCLK
+ 100
LVDS Output Enable Time
tLVEN
From the last bit of the enable UART
packet to VOS = 1125mV
100
F
s
LVDS Output Disable Time
tLVDS
From the last bit of the enable UART
packet to VOS = 0V
100
F
s
Deserializer Delay
tSD
Figure 8 (Note 4)
3540
Bits
Reverse Control-Channel Output
Rise Time
tR
No forward-channel data transmission
(Figure 1)
180
400
ns
Reverse Control-Channel Output
Fall Time
tF
No forward-channel data transmission
(Figure 1)
180
400
ns
Lock Time
tLOCK
Figure 9
3.6
ms
Power-Up Time
tPU
Figure 10
4.1
ms
I2S OUTPUT TIMING
WS Jitter
tAJ-WS
tWS = 1/fWS,
rising (falling)
edge to falling
(rising) edge
(Note 5)
fWS = 48kHz or 44.1kHz
0.4e-3
x tWS
0.5e-3
x tWS
ns
fWS = 96kHz
0.8e-3
x tWS
1e-3
x tWS
fWS = 192kHz
1.6e-3
x tWS
2e-3
x tWS
SCK Jitter
tAJ-SCK
tSCK = 1/fSCK,
rising edge to
rising edge
nWS = 16 bits, fWS =
48kHz or 44.1kHz
13e-3
x tSCK
16e-3
x tSCK
ns
nWS = 24 bits, fWS =
96kHz
39e-3
x tSCK
48e-3
x tSCK
nWS = 32 bits,
fWS = 192kHz
0.1
x tSCK
0.13
x tSCK
Audio Skew Relative to Video
tASK
Video and audio synchronized
3 x tWS 4 x tWS
F
s
SCK, SD, WS Rise-and-Fall Time
tR, tF
20% to 80%
CL = 10pF, DCS = 1
0.3
3.1
ns
CL = 5pF, DCS = 0
0.4
3.8
SD, WS Valid Time Before SCK
tDVB
tSCK = 1/fSCK (Figure 11)
0.35 x
tSCK
0.5 x
tSCK
ns
SD, WS Valid Time After SCK
tDVA
tSCK = 1/fSCK (Figure 11)
0.35 x
tSCK
0.5 x
tSCK
ns



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