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SC197 Datasheet(PDF) 16 Page - Semtech Corporation |
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SC197 Datasheet(HTML) 16 Page - Semtech Corporation |
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16 / 20 page ![]() SC197 16 C OUT Selection The internal voltage loop compensation in the SC197 limits the minimum output capacitor value to 10μF. This is due to its influence on the the loop crossover frequency, phase margin, and gain margin. Increasing the output capacitor above this minimum value will reduce the cross- over frequency and provide greater phase margin. The output capacitor determines the output voltage ripple and contributes load current during large step load transitions. A capacitor between 10μF and 22μF will usually be adequate in stabilizing the output during large load transitions. Capacitors with X7R or X5R ceramic dielectric are recom- mended for their low ESR and superior temperature and voltage characteristics. Y5V capacitors should not be used as their temperature coefficients make them unsuitable for this application. In addition to ensuring stability, the output capacitor serves other important functions. This capacitor deter- mines the output voltage ripple — as capacitance increases, ripple voltage decreases. It also supplies current during a large load step for a few switching cycles until the control loop responds (typically 3 switching cycles). Once the loop responds, regulation is restored and the desired output is reached. During the period prior to PWM operation resuming, the relationship between output voltage and output capacitance can be approximated using the following equation. f V I 3 C DROOP LOAD OUT This equation can be used to approximate the minimum output capacitance needed to ensure voltage does not droop below an acceptable level. For example, a load step from 50mA to 400mA requiring droop less than 50mV would require the minimum output capacitance to be as follows. F 0 . 6 10 4 05 . 0 4 . 0 3 C 6 OUT Applications Information (continued) In this example, using a standard 10µF capacitor would be adequate to keep voltage droop less than the desired limit. Note that if the voltage droop limit were decreased from 50mV to 25mV, the output capacitance would need to be increased to at least 12µF (twice as much capaci- tance for half the droop). Capacitance will decrease from the nominal value when a ceramic capacitor is biased with a DC current, so it is important to select a capacitor whose value exceeds the necessary capacitance value at the pro- grammed output voltage. Check the manufacturer’s capacitance vs. DC voltage graphs when selecting an output capacitor to ensure the capacitance will be adequate. Table 3 lists the manufacturers of recommended output capacitor options. Table 3 — Recommended Output Capacitors Manufacturer Part Nunber Value (μF) Type Rated Voltage (VDC) Dimensions LxWxH (mm) Case Size Murata GRM188R60J106ME47D 10±20% X5R 6.3 1.6x0.8x0.8 0603 Murata GRM21BR60J106K 10±10% X5R 6.3 2.0x1.25x1.25 0805 TaiyoYuden JMK107BJ106MA-T 10±20% X5R 6.3 1.6x0.8x0.8 0603 TDK C1608X5R0J106MT 10±20% X5R 6.3 1.6x0.8x0.8 0603 C IN Selection The SC197 input source current will appear as a DC supply current with a triangular ripple imposed on it. To prevent large input voltage ripple, a low ESR ceramic capacitor is required. A minimum value of 4.7μF should be used. It is important to consider the DC voltage coefficient charac- teristics when determining the actual required value. For example, a 10μF, 6.3V, X5R ceramic capacitor with 5V DC applied may exhibit a capacitance as low as 4.5μF. The value of required input capacitance is estimated by deter- mining the acceptable input ripple voltage and calculating the minimum value required for C IN using the equation f ESR I V V V 1 V V C OUT IN OUT IN OUT IN |
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