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ICS9LP525-2 Datasheet(PDF) 17 Page - Integrated Device Technology |
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ICS9LP525-2 Datasheet(HTML) 17 Page - Integrated Device Technology |
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17 / 21 page ![]() IDTTM/ICSTM PC MAIN CLOCK 1397—11/08/10 ICS9LP525-2 PC MAIN CLOCK 17 Byte 12 Byte Count Register Bit Pin Name Description Type 0 1 Default 7 Reserved RW 0 6 Reserved RW 0 5 BC5 RW 0 4 BC4 RW 0 3 BC3 RW 1 2 BC2 RW 1 1 BC1 RW 0 0 BC0 RW 1 Byte 13 to 28 Reserved Byte 29 Slew Rate Control Bit Pin Name Description RW 0 1 Default 7 USB_Slew1 USB Slew Rate Control (MSB) RW 1 6 USB_Slew0 USB Slew Rate Control (LSB) RW 0 5 PCI_Slew1 PCI Slew Rate Control (MSB) RW 1 4 PCI_Slew0 PCI Slew Rate Control (LSB) RW 1 3 Reserved RW 1 2 REF Slew Rate Changes Ref Slew Rate RW 1.2V/ns 2.2V/ns 1 1 Reserved RW 0 Read Back byte count register, max bytes = 32 See Slew Rate Selection Table See Slew Rate Selection Table |
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