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ICS9LP525-2 Datasheet(PDF) 12 Page - Integrated Device Technology |
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ICS9LP525-2 Datasheet(HTML) 12 Page - Integrated Device Technology |
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12 / 21 page ![]() IDTTM/ICSTM PC MAIN CLOCK 1397—11/08/10 ICS9LP525-2 PC MAIN CLOCK 12 PCI_STOP# Power Management SMBus OE Bit PCI_STOP# Stoppable Free running Stoppable Free running 1 Running Running Running Running CK= High CK# = Low Running CK= Pull down CK# = Low Running Disable X CPU_STOP# Power Management SMBus OE Bit PCI_STOP# Stoppable Free running 1 Running Running CK= High CK# = Low Running CK= Pull down CK# = Low Running Disable X CR# Power Management SMBus OE Bit CR# Stoppable Free running 1 Running Running 0 Disable X PD# Power Management Device State w/o Latched input w/Latched input Latches Open Power Down M1 Virtual Power Cycle to Latches Open CPU1 CK= Pull down, CK# = Low CK= Pull down, CK# = Low CK= Pull down, CK# = Low Running Differential Clocks (Except CPU1) CK= Pull down CK# = Low Enable CK= Pull down, CK# = Low CK= Pull down, CK# = Low Low Hi-Z Single-ended Clocks CK= Pull down CK# = Low CK= Pull down CK# = Low Enable 0 CK= Pull down, CK# = Low Low Enable 0 Low Low Single-ended Clocks Differential Clocks (Except CPU) Low CK = Pull down, CK# = Low Differential Clocks Differential Clocks |
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