ICS9LP525-2 datasheet(18/21 Pages) IDT

Part #	ICS9LP525-2

Description	56-pin CK505 for Intel Desktop Systems

PDF	21 Pages

Scroll/Zoom	100%

Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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18 / 21 page

IDTTM/ICSTM PC MAIN CLOCK

1397—11/08/10

ICS9LP525-2

PC MAIN CLOCK

Test Clarification Table

Comments

FSLC/

TEST_SEL

HW PIN

FSLB/

TEST_MODE

HW PIN

TEST

ENTRY BIT

B9b3

REF/N or

HI-Z

B9b4

OUTPUT

<2.0V

NORMAL

>2.0V

HI-Z

>2.0V

REF/N

>2.0V

REF/N

>2.0V

REF/N

<2.0V

HI-Z

<2.0V

REF/N

Power-up w/ TEST_SEL = 1 to enter test mode

Cycle power to disable test mode

FSLC./TEST_SEL -->3-level latched input

If power-up w/ V>2.0V then use TEST_SEL

If power-up w/ V<2.0V then use FSLC

FSLB/TEST_MODE -->low Vth input

TEST_MODE is a real time input

If TEST_SEL HW pin is 0 during power-up,

test mode can be invoked through B9b3.

If test mode is invoked by B9b3, only B9b4

is used to select HI-Z or REF/N

FSLB/TEST_Mode pin is not used.

Cycle power to disable test mode, one shot control

B9b3: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION)

B9b4: 1= REF/N, Default = 0 (HI-Z)

ICS9LP525-2 Datasheet(PDF) 18 Page - Integrated Device Technology

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