©2011 Silicon Storage Technology, Inc.

S71327-04-000

02/11

19

32 Mbit SPI Serial Flash

SST25VF032B

Data Sheet

A Microchip Technology Company

Enable-Write-Status-Register (EWSR)

The Enable-Write-Status-Register (EWSR) instruction arms the Write-Status-Register (WRSR)

instruction and opens the status register for alteration. The Write-Status-Register instruction must be

executed immediately after the execution of the Enable-Write-Status-Register instruction. This two-

step instruction sequence of the EWSR instruction followed by the WRSR instruction works like soft-

ware data protection (SDP) command structure which prevents any accidental alteration of the status

register values. CE# must be driven low before the EWSR instruction is entered and must be driven

high before the EWSR instruction is executed.

Write-Status-Register (WRSR)

The Write-Status-Register instruction writes new values to the BP3, BP2, BP1, BP0, and BPL bits of

the status register. CE# must be driven low before the command sequence of the WRSR instruction is

entered and driven high before the WRSR instruction is executed. See Figure 19 for EWSR or WREN

and WRSR instruction sequences.

Executing the Write-Status-Register instruction will be ignored when WP# is low and BPL bit is set to

‘1’. When the WP# is low, the BPL bit can only be set from ‘0’ to ‘1’ to lock-down the status register, but

cannot be reset from ‘1’ to ‘0’. When WP# is high, the lock-down function of the BPL bit is disabled and

the BPL, BP0, and BP1 and BP2 bits in the status register can all be changed. As long as BPL bit is

the WRSR instruction, the bits in the status register can all be altered by the WRSR instruction. In this

case, a single WRSR instruction can set the BPL bit to ‘1’ to lock down the status register as well as

altering the BP0, BP1, and BP2 bits at the same time. See Table 2 for a summary description of WP#

and BPL functions.

Figure 19:Enable-Write-Status-Register (EWSR) or Write-Enable (WREN) and Write-Sta-

tus-Register (WRSR) Sequence

1327 F20.0

MODE 3

HIGH IMPEDANCE

MODE 0

STATUS

REGISTER IN

7 6 5 4321 0

MSB

MSB

MSB

01

MODE 3

SCK

SI

SO

CE#

MODE 0

50 or 06

0 1 2 3 4 5 6 7

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15