SC1405

HIGH SPEED SYNCHRONOUS POWER

MOSFET SMART DRIVER

© 2000 SEMTECH CORP.

652 MITCHELL ROAD NEWBURY PARK CA 91320

August 31, 2000

10

ably less than .1” away. This capacitor will be added to

Ciss in the above equation to reduce the effective spike

voltage, Vspike.

The selection of the bottom MOSFET must be done with

attention paid to the Crss/Ciss ratio. A low ratio reduces

the Miller feedback and thus reduces Vspike. Also

MOSFETs with higher Turn-on threshold voltages will

conduct at a higher voltage and will not turn on during

the spike. The MOSFET shown in the schematic (figure

3) has a 2 volt threshold and will require approximately 5

volts Vgs to be conducting, thus reducing the possibility

of shoot-through. A zero ohm bottom FET gate resistor

will obviously help keeping the gate voltage low.

Ultimately, slowing down the top FET by adding gate re-

sistance will reduce di/dt which will in turn make the ef-

fective impedance of the capacitors higher, thus allowing

the BG driver to hold the bottom gate voltage low. It

does this at the expense of increased switching times (

and switching losses) for the top FET.

RINGING ON THE PHASE NODE

The top MOSFET source must be close to the bottom

MOSFET drain to prevent ringing and the possibility of

the phase node going negative.

This frequency is de-

termined by:

F

Where:

L

added to trace inductance of the connection between top

FET’s source and the bottom FET’s drain added to the

trace resistance of the bottom FET’s ground connection.

Coss=Drain to source capacitance of bottom FET. If

there is a Schottky used, the capacitance of the Schottky

is added to the value.

Although this ringing does not pose any power losses

due to a fairly high Q, it could cause the phase node to

go too far negative, thus causing improper operation,

double pulsing or at worst driver damage. This ringing is

also an EMI nuisance due to its high resonant frequency.

Adding a capacitor, typically 1000-2000pf, in parallel with

Coss can often eliminate the EMI issue. If double puls-

ing is caused due to excessive ringing, placing 4.7-10

ohm resistor between the phase node and the DRN pin

of the SC1405 should eliminate the double pulsing.

Proper layout will guarantee minimum ringing and elimi-

nate the need for external components. Use of SO-8 or

other surface mount MOSFETs will reduce lead induc-

tance as well as radiated EMI.

ASYNCHRONOUS OPERATION

The SC1405 can be configured to operate in Asyn-

chronous mode by pulling S-MOD to logic LOW, thus

disabling the bottom FET drive. This has the effect of

saving power at light loads since the bottom FET’s

gate capacitance does not have to charged at the

switching frequency. There can be a significant sav-

ings since the bottom driver can supply up to 2A pulses

to the FET at the switching frequency. There is an ad-

ditional efficiency benefit to operating in asynchronous

mode. When operating in synchronous mode, the in-

ductor current can go negative and flow in reverse di-

rection when the bottom FET is on and the DC load is

less than 1/2 inductor ripple current. At that point, the

inductor core and wire losses, depending on the mag-

nitude of the ripple current, can be quite significant.

Operating in asynchronous mode at light loads effec-

tively only charges the inductor by as much as needed

to supply the load current, since the inductor never

completely discharges at light loads. DC regulation

can be an issue depending on the type of controller

used and minimum load required to maintain regula-

tion. If there are no Schottkys used in parallel with bot-

tom FET, the FET’s body diode will need to conduct in

asynchronous mode. The high voltage drop of this

diode must be considered when determining the crite-

ria for this mode of operation.

DSPS DR

This pin produces an output which is a logical duplicate

of the bottom FET’s gate drive, if S-MOD is held LOW.

OVP_S/OVER TEMP SHUTDOWN

Output over-voltage protection may be implemented on

the SC1405 independent of the PWM controller . A

voltage divider from the output is compared with the

internal bandgap voltage of 1.2V (typical). Upon ex-

ceeding this voltage, the overvoltage comparator dis-

ables the top FET, while turning on the bottom FET to

allow discharge of the output capacitors excessive volt-

age through the output inductor. There should be suffi-

cient RC time constant as well as voltage headroom on

the OVP_S pin to assure it does not enter overvoltage

mode inadvertently. The SC1405 will shutdown if its Tj

exceeds 165 °C.