LH28F016LL datasheet(6/29 Pages) SHARP

6 / 29 page

LH28F016LL

16M (1M × 16, 2M × 8) Flash Memory

Figure 3. LH28F016LL Memory Map

MEMORY MAP

The LH28F016LL contains three types of Status

Registers to accomplish various functions:

• A Compatible Status Register (CSR) which is 100%

compatible with the LH28F008SA Flash memory’s

Status Register. This register, when used alone, pro-

vides a straightforward upgrade capability to the

LH28F016LL from a LH28F008SA-based design.

• A Global Status Register (GSR) which informs

the system of command Queue status. Page

Buffer status, and overall Write Status Machine

(WSM) status.

• 32 Block Status Registers (BSRs) which provide

block-specific status information such as the block

lock-bit status.

The GSR and BSR memory maps for Byte-Wide and

Word-Wide modes are shown in Figures 4 and 5.

The LH28F016LL incorporates an open drain

»/BY » output pin. This feature allows the user to OR-

tie many RY

»/BY » pins together in a multiple memory con-

figuration such as a Resident Flash Array.

The LH28F016LL also incorporates a dual chip-

enable function with two input pins, CE

»0 and CE »1.These

pins have exactly the same functionality as the regulary

chip-enable pin CE

» on the LH28F008SA. For minimum

chip designs, CE

»1 may be tied to ground and use CE »0

as the chip enable input.The LH28F016LL uses the logi-

cal combination of these two signals to enable or dis-

able the entire chip. Both CE

»0 and CE »1 must be active

low to enable the device and if either one becomes in-

active, the chip will be disabled. This feature, along with

the open drain RY

»/BY » pin, allows the system designer

to reduce the number of control pins used in a large

array of 16M devices.

The BY

»TE » pin allows either x8 or x16 read/writes to

the LH28F016LL. BY

»TE » at logic low selects 8-bit mode

with address A0 selecting between low byte and high

byte. On the other hand, BY

»TE » at logic high enables

16-bit operation with address A1 becoming the lowest

order address and address A0 is not used (don’t care).

A device diagram is shown in Figure 1.

The LH28F016LL is specified for a maximum access

time (tACC)150 ns, in operating voltage 2.7 V to 3.6 V

and in operating temperature 0°C to +70°C.

The LH28F016LL incorporates an Automatic Power

Saving (APS) feature which substantially reduces the

active current when the device is in static mode of

operation (address not switching).

In APS mode, the typical ICC current is 1 mA at 3.0 V.

A Deep Power-Down mode of operation is invoked

when the RP

» (called PWD on the LH28F008SA) pin

transitions low. This mode brings the device power con-

sumption to less than 5 µA typically, and provides addi-

tional write protection by acting as a device reset pin

during power transitions. A reset time of 480 ns is re-

quired from RP

» switching high until outputs are again

valid. In the Deep Power-Down state, the WSM is reset

(any current operation will abort) and the CSR, GSR

and BSR registers are cleared.

A CMOS Standby mode of operation is enabled when

either CE

»0 or CE »1 transitions high and RP » stays high

with all input control pins at CMOS levels. In this mode,

the device typically draws an ICC standby current of

10 µA.

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