TLK100 datasheet(66/88 Pages) TI

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TLK100

SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009

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8.5.19 TDR Pattern Control Register 2 (TDRLCR2)

This register allows configuring the gear threshold values for the TDR test.

Table 8-48. TDR Pattern Control Register 2 (TDRLCR2), address 0x0C0C

BIT

NAME

DEFAULT

FUNCTION

15:9

Reserved

0,RO

Ignore on read

8:4

cfg_ptrn_gear_tout

0x14,RW

Thresholds gear shifts distance in samples

3:0

Reserved

0x8,RO

Ignore on read

8.5.20 DSA Configuration Register 1 (DSACR1)

This register allows use of the smoothing filter during the DSA tests.

Table 8-49. DSA Configuration Register 1 (DSACR1), address 0x0C26

BIT

NAME

DEFAULT

FUNCTION

15:7

Reserved

0x180,RO

Ignore on read

cfg_dsa_smooth_filt_byps

0x1,RW

0 = Disable DSA engine smooth filter bypass

1 = Enable DSA engine smooth filter bypass

5:0

Reserved

0x04,RO

Ignore on read

8.5.21 DSA Configuration Register 2 (DSACR2)

This register allows configuration of the DSA taps are used for the DSA tests. We specify the first and last

taps in use and the DSA uses all the taps between them.

Table 8-50. DSA Configuration Register 2 (DSACR2), address 0x0C27

BIT

NAME

DEFAULT

FUNCTION

15:8

cfg_dsa_en_last_coeff_num

0x1E,RW

Last coefficient number used by the DSA engine

7:0

cfg_dsa_en_first_coeff_num

0x0,RW

First coefficient number used by the DSA engine

8.5.22 DSA Start Frequency (DSASFR)

This register allows configuration of the starting frequency for the spectrum analysis of the DSA engine. It

represents 1.9 kHz resolution in the frequency domain.

Table 8-51. DSA Start Frequency (DSASFR), address 0x0C28

BIT

NAME

DEFAULT

FUNCTION

15:0

cfg_start_freq

0x0,RW

Starting frequency for the DSA

8.5.23 DSA Frequency Control (DSAFCR)

This register defines the average factor we will use in the DSA. In addition it defines the frequency step for

the DSA. The field represents resolution of 119.2 Hz.

Table 8-52. DSA Frequency Control (DSAFCR), address 0x0C29

BIT

NAME

DEFAULT

FUNCTION

15:12

cfg_dsa_average

0xA,RW

Averaging factor for DSA engine – 2X cycles

Reserved

0x0,RO

Reserved

10:0

cfg_dsa_inc_factor

0x400,RW

DSA Frequency increment factor (frequency step)

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