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MII_TX_CLK

MII_TX_EN

MII_TXD[3:0]

MII_RX_CLK

MII_RX_DV

MII_RX_ERR

MII_RXD[3:0]

MII_CRS

MII_COL

TLK100

MAC

TX_CLK

TX_EN

TXD[3:0]

RX_CLK

RX_DV

RX_ER

RXD[3:0]

CRS

COL

TLK100

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SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009

Interfaces

4.1

Media Independent Interface (MII)

The Media Independent Interface (MII) is a synchronous 4-bit wide nibble data interface that connects the

PHY to the MAC in 100B-TX and 10B-T modes. The MII is fully compliant with IEEE802.3-2002 clause 22.

The MII consists of the data signals MII_TXD[3:0] and MII_RXD[3:0], transmit and receive valid signals

MII_TX_EN and MII_RX_DV, error signal MII_RX_ERR and transmit/receive clocks MII_TX_CLK and

MII_RX_CLK. In addition, the interface consists of asynchronous line status signals MII_CRS and

MII_COL, indicating carrier sense and collision. Data on MII_TXD[3:0] and MII_RXD[3:0] are latched with

reference to the edges of MII_RX_CLK and MII_TX_CLK clocks respectively as defined in the MII timing

diagrams 22-14 and 22-15 of IEEE802.3-2002 clause 22. Both clocks are sourced by the PHY. In

100B-TX mode, the MII_RX_CLK and MII_TX_CLK source 25MHz clocks and in 10B-T, they source

2.5MHz clocks.

Figure 4-1 describes the MII signals connectivity.

Figure 4-1. MII Signaling

The isolate register 0.10 defined in IEEE802.3-2002 used to electrically isolate the PHY from the MII (if

set, all transactions on the MII interface are ignored by the PHY).

Additionally, the MII interface includes the carrier sense signal MII_CRS, as well as a collision detect

signal MII_COL. The MII_CRS signal asserts to indicate the reception of data from the network or as a

function of transmit data in Half Duplex mode. The MII_COL signal asserts as an indication of a collision

which can occur during half-duplex operation when both transmit and receive operation occur

simultaneously.

Interfaces

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