LS027B7DH01 datasheet(19/32 Pages) SHARP

19 / 32 page

SPEC No.

LCY-1210401A

MODEL No.

LS027B7DH01

PAGE

6-5-2 Data Update Mode (Multiple Lines)

Updates arbitrary multiple lines data. (M0=”H”、M2＝”L”)

M0: Mode flag. Set for “H”. Data update mode (Memory internal data update)

When “L”, display mode (maintain memory internal data).

M1: Frame inversion flag.

When “H”, outputs VCOM=”H”, and when “L”, outputs VCOM=”L”.

When EXTMODE=”H”, it can be “H” or “L”.

M2: All clear flag.

Refer to 6-5-4) All Clear Mode to execute clear.

DUMMY DATA: Dummy data. It can be “H” or “L” (“L” is recommended.)

* For gate line address setting, refer to 6-6) Input Signal and Display.

* Input data continuously.

* M1: Frame inversion flag is enabled when EXTMODE=”L”.

* When SCS becomes “L”, M0 and M2 are cleared.

SCS

DUMMY DATA(don't care)

SCLK

DUMMY DATA(don't care)

DMY

D399

D400

D398

AG0

AG1

AG2

DMY

AG1

AG0

D397

D400

D398

D399

AG7

AG6

AG5

AG3

AG7

AG6

AG5

AG4

D399

AG7

AG6

AG5

AG4

AG0

AG1

D400

tsSI

thSI

tsSCS

GL1st line

Date write period

(400ck)

GL2nd line

Mode select period

(3ck+5ckDMY)

GL(n)th line

Date write period

(400ck)

Date transfer period

(16ck)

GL(n-1)th line

thSCS

twSCLKH

twSCLKL

twSCSL

twSCSH

Gate line address select period

(8ck)

Gate line address select period

(8ck(Dummy)+8ck(address)=16ck)

Date transfer period

(8ck(Dummy)+8ck(address)=16ck)

※

Data write period

Data is being stored in 1

st latch block of binary driver on panel.

※

Data transfer period

For example, during GL2nd line data transfer period, GL 2

nd line address is latched and GL1st

line data is transferred from 1

st latch to pixel internal memory circuit at the same time.

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