DS80C390 datasheet(3/53 Pages) DALLAS

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DS80C390 Dual CAN High-Speed Microprocessor

3 of 53

AC ELECTRICAL CHARACTERISTICS—(MULTIPLEXED ADDRESS/DATA BUS)

(Note 10, Note 11)

40MHz

VARIABLE CLOCK

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

MIN

MAX

UNITS

External oscillator

Oscillator Frequency

1 / tCLCL

External crystal

MHz

ALE Pulse Width

tLHLL

0.375 tMCS

- 5

Port 0 Instruction Address or

CE0–4

Valid to ALE Low

tAVLL

0.125 tMCS - 5

Address Hold After ALE Low

tLLAX1

0.125 tMCS - 5

ALE Low to Valid Instruction In

tLLIV

0.625 tMCS - 20

ALE Low to

PSEN Low

tLLPL

0.125 tMCS - 5

PSEN Pulse Width

tPLPH

0.5 tMCS - 8

PSEN Low to Valid Instruction In

tPLIV

0.5 tMCS - 20

Input Instruction Hold After

PSEN

tPXIX

Input Instruction Float After

PSEN

tPXIZ

0.25 tMCS - 5

Port 0 Address to Valid Instruction In

tAVIV1

0.75 tMCS - 22

Port 2, 4 Address to Valid Instruction

tAVIV2

0.875 tMCS - 30

PSEN Low to Address Float

tPLAZ

Note 11:

All parameters apply to both commercial and industrial temperature operation unless otherwise noted. The value tMCS is a function

of the machine cycle clock in terms of the processor’s input clock frequency. These relationships are described in the Stretch Value

Timing

table. All signals characterized with load capacitance of 80pF except Port 0, ALE,

PSEN, RD, and WR with 100pF.

Interfacing to memory devices with float times (turn off times) over 25ns can cause bus contention. This does not damage the

parts, but causes an increase in operating current. Specifications assume a 50% duty cycle for the oscillator. Port 2 and ALE timing

changes in relation to duty cycle variation. Some AC timing characteristic drawings contain references to the CLK signal. This

waveform is provided to assist in determining the relative occurrence of events and cannot be used to determine the timing of

signals relative to the external clock. AC timing is characterized and guaranteed by design but is not production tested.

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